Specifications

Rev. 2.1 EPSON 6–57
S1D12400 Series
S1D12400
Series
E
A0,CS
D0 to D7
tCYC6
tEWL
tAW6 tEWH
tAH6
tDH6tDS6
System Bus Write Characteristics II (68 series MPU)
Item Signal Symbol
Measuring
Min. Max. Unit
condition
System cycle time A0, CS t
CYC6 – 300 – ns
Address setup time t
AW6 60 – ns
Address hold time t
AH6 30 – ns
Data setup time D0 to D7 t
DS6 –60–ns
Data hold time t
DH6 –50–ns
Enable HIGH pulse width E t
EWH –60–ns
Enable LOW pulse width E t
EWL –60–ns
[VSS = –5.5 V to –4.5 V, Ta = –30 to 85°C unless otherwise specified]
*1: tCYC6 indicates the cycle of the E signal in the CS active state.
It is necessary to secure
tCYC6 after CS becomes active.
*2: For the rise and fall time of input signals, set 15 ns or less.
*3: Every timing is specified on 20% and 80% of V
SS.
*4: The same timing is not required for A0 and CS. Input signals so that A0 and CS may satisfy
tAW6 and tAH6
respectively.
Item Signal Symbol
Measuring
Min. Max. Unit
condition
System cycle time A0, CS t
CYC6 – 500 – ns
Address setup time t
AW6 60 – ns
Address hold time t
AH6 30 – ns
Data setup time D0 to D7 t
DS6 – 100 – ns
Data hold time t
DH6 –50–ns
Enable HIGH pulse width E t
EWH – 100 – ns
Enable LOW pulse width E t
EWL – 100 – ns
[VSS = –4.5 V to –2.4 V, Ta = –30 to 85°C unless otherwise specified]
Item Signal Symbol
Measuring
Min. Max. Unit
condition
System cycle time A0, CS t
CYC6 – 1000 – ns
Address setup time t
AW6 60 – ns
Address hold time t
AH6 30 – ns
Data setup time D0 to D7 t
DS6 – 200 – ns
Data hold time t
DH6 –50–ns
Enable HIGH pulse width E t
EWH – 200 – ns
Enable LOW pulse width E t
EWL – 200 – ns
[VSS = –2.4 V to –1.8 V, Ta = –30 to 85°C unless otherwise specified]