Specifications

Rev. 2.4 EPSON 5–9
S1D12304/12305 Series
S1D12304/12305
Series
Pin name I/O Description No. of Pins
D7 (SI) I 8-bit input data bus. These pins are connected to a 8-bit or 16-bit 8
D6 (SCL) standard MPU data bus.
D5 to D0 When P/S = LOW, the D7 and D6 pins are operated as a serial data
input and a serial clock input respectively.
When P/S = LOW, be sure to fix D5 to D0 to HIGH or LOW.
A0 I Usually, this pin connects the least significant bit of the MPU address 1
bus and identifies a data command.
0 : Indicates that D0 to D7 are a command.
1 : Indicates that D0 to D7 are display data.
RES I In case of a 68 series MPU, initialization can be performed by 1
changing RES
. In case of an 80 series MPU, initialization can
be performed by changing
.
A reset operation is performed by edge sensing of the RES signal.
An interface type for the 68/80 series MPU is selected by input level
after initialization.
LOW : 80 series MPU interface
HIGH : 68 series MPU interface
CS I Chip select signal. Usually, this pin inputs the signal obtained by 1
decoding an address bus signal. At the LOW level, this pin is
enabled.
WR (E) I <When connecting an 80 series MPU>
Active LOW. This pin connects the WR signal of the 80 series 1
MPU. The signal on the data bus is fetched at the rise of the WR
signal.
When P/S = LOW, be sure to fix the WR signal to HIGH or LOW.
<When connecting a 68 series MPU>
Active HIGH. This pin becomes an enable clock input of the 68
series MPU.
P/S I This pin switches between serial data input and parallel data input. 1
IF I Interface data length select pin for parallel data input. 1
HIGH: 8-bit parallel input
LOW: 4-bit parallel input
When P/S = LOW, connect this pin to V
DD or VSS.
Pins for System Bus Connection
P/S D7 D6 D5 to D0 CS A0
LOW SI SCL — CS A0
HIGH D7 D6 D5 to D0 CS A0
P/S Chip Select Data/Command Data Serial Clock
HIGH CS A0 D0 to D7 –
LOW CS A0 SI SCL