Specifications

5–2 EPSON Rev. 2.4
S1D12304/12305 Series
3. BLOCK DIAGRAM
Input buffer
MPU interface
Address counter
Command
decoder
Cursor control
SEG driving circuit COM driving circuit
Refresh address counter
RAM
CG ROM
Timing generating circuit
Oscillator
Power circuit
IF
RES
CS
WR (E)
P/S
A0
SEG1 to 60 SEGS2, 6
COM1 to 28 COMS2, 3
V
1
V
2
V
3
V
4
V
5
CAP1+ CAP1– CAP2+ CAP2– V
R
V
OUT
V
S1
D6 (SCL)
D0 D1 D2 D3 D4 D5 D7 (SI)