Specifications
REV.-A
2.3.6 Printhead Drive Circuit
Figure 2-43 shows the
printhead
drive circuit.
The print data developed by CPU is transferred to the head control gate array -
E05A65 (ICI 2) via data
bus. The data for 48 nozzles stored in
E05A65 is serially transmitted from HDDAT port to the head
driver -
~PD 1632
(IC8,9).
HDCLK
is a clock for this serial transmission. The E05A65 transmits
HDSTB
signal as soon as the data transmission for 48 nozzles is completed.
The head is controlled by
CHG
and
DSCHG
pulses.
CPU
(IC5)
+35V
D
VH supply
+
VH
circuit
Thermistor
Bus
1-
E
I-J
PTS
E05A48 (IC1O)
—
—
uPDI 6322
(IC6,9)
r
1
1
CHG
STB
BLK
CLK
B
---
CHG
STB
BLK
---
I
-=1
CLK
A
I
+B
I
L~
+
VH
Charge
Circuit
E05A65
(IC12)
ALDCHG
HDSTB
DSCHG
HDCLK
I
I
I
I
I
++
I
I
I
i
I
I
I
I
I
++
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
i
I
Print
head
Figure 2-43. Printhead Drive Circuit
The
printhead
drive circuit can be divided into two circuits:
Charge/discharge circuit and
Printhead
““,
(
voltage supply circuit.
c1
.
.-
.
.
.
.
.
.
2-34