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SED1278

LCD Controller/Drivers

Technical Manual

Summary of content (41 pages)

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SED1278 LCD Controller/Drivers Technical Manual
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Contents OVERVIEW ......................................................................................................................................................... 9–1 FEATURES .......................................................................................................................................................... 9–1 BLOCK DIAGRAM ...............................................................................................................................................
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SED1278 OVERVIEW FEATURES The SED1278 is a dedicated character display controller/ driver which, when used with the SED1181F or the SED1681 segment drivres, is able to display up to 80 characters under 4- or 8-bit MPU control. The internal character generator (CG) ROM has an extended 240, 5×10 pixel, character set, plus CGRAM space for an additional eight user definable 5×8 pixel characters.
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SED1278 BLOCK DIAGRAM OSC1 Instruction Decoder Cursor/ Printer Control Address Counter ACC I/O Buffer Instruction Register DB 0 to DB 7 I/O Control R/W RS Oscillation Circuit Refresh Address Counter 7 Daia Register E OSC2 7 MPX Timing Generator Display Data RAM DDRAM 80 Bytes Shift Register 16 Bits XSCL LP FR Common Driving Output Circuit 8 MPX Character Generator RAM (CGRAM) 64 Bits VSS VDC V1 Character Generator RAM (CGROM) 5 x 10 x 240 Bits 5 COM 1 to COM 16 SEG 1 to SEG 40 Segm
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SED1278 24 1 25 80 SED1278D 40 65 41 64 PINOUT Name SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 Number 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin Pin Name SEG2 SEG1 GND OSC1 OSC2 V1 V2 V3 V4 V5 LP XSCL VDD FR DO RS R/W E DB0 DB1 Number 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 EPSON Name DB2 DB3 DB4 DB5 DB6 DB7 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14
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SED1278 PIN DESCRIPTION MPU Interface RS R/W E Register select signal input. Selects between the data and instruction registers during CPU access. RS = 0: Instruction register access cycle RS = 1: Data register access cycle This input selects between SED1278 register read and write cycles. R/W = 0: Register write cycle R/W = 1: Register read cycle Read/write execute signal input. DB0 to DB7 TTL level data input/output lines, for connection to the system MPU data bus.
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SED1278 TERMINAL CONFIGURATION 1. Input terminal configuration (1) VDD Applicable terminal ·E · OSCI Internal VSS 2. Input terminal configuration (2) With pull-up MOS resistor VDD Applicable terminal · RS, R/W Internal VSS Output terminal configuration VDD Applicable terminal · OSC2 · XSCL, LP, FR, DO SED1278 3.
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SED1278 4. Input/Output terminal configuration VDD Applicable terminal · DBO to DB7 Internal VSS INSTRUCTION DESCRIPTION Instruction Summary Instruction Clear Display Code RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 Description Cycle Time (max.) 1 Clears all display data and sets DDRAM address 0 in the address counter. 410 clocks 410 clocks Return Home 0 0 0 0 0 0 0 0 1 * Set DDRAM address 0 in the address counter. Also returns any shifted data to home.
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SED1278 Write Only Instructions writing the CGRAM always shifts the cursor. Note that if a two line display is used both lines will be shifted simultaneously. Clear Display DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 01H Display ON/OFF This instruction 1. loads all locations in the display data (DD) RAM with 20H. 2. clears the contents of the address counter to 0H. 3. sets the display for zero character shift. 4. sets the address counter to point to the DDRAM. 5.
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SED1278 TABLE 2 Combinations of Display Lines and Duty Cycle N F Number of Line Duty Ratio Common Output Signal 0 0 1 line 1/8 COM1 to COM8 COM9 to COM16 0 1 1 line 1/11 COM1 to COM11 COM12 to COM16 1 * 2 lines 1/16 COM1 to COM16 — TABLE 3 Valid CGRAM Address Ranges Set CGRAM Address DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 ACR This instruction 1. loads a new 6-bit address into the address counter. 2. sets the address counter to address CGRAM.
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SED1278 Read Only Instructions Read Busy Flag/Address Counter Read Data DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BF ACC DATA RS = 1 Reading the instruction register yields the current value of the address counter and the busy flag. This instruction must be executed prior to any other instructions. • ACC, the address counter value, will point to a location in either CGRAM or DDRAM, depending on the type of “Set RAM Address” instruction last sent.
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SED1278 SPECIFICATIONS Absolute Maximum Ratings Parameter Symbol Rating Unit Supply voltage (1) VDD –3 to +7.0 V Supply voltage (2)* V1 to V5 –0.3 to VDD+0.3 V Input voltage VIN –0.3 to VDD+0.3 V Operating temperature Topr –20 to +75 °C Storage temperature Tstg –65 to +150 °C Soldering temperature × time** Tsol 260, 10 °C, s Power dissipation PD 300 mW Notes: 1. VDD > V1 > V2 > V3 > V4 > V5 > VSS 2.
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SED1278 AC Characteristics • MPU write cycle timing (write to SED1278) RS VIH1 VIL1 tAH tAS R/W VIL1 tWEH tAH tFE VIH1 E VIL1 tDS trE VIH1 VIL1 DB0 to DB7 tDH Valid Data tcycE (VDD = 5.
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SED1278 (VDD = 5.0 V ± 10%, VSS = 0 V, Ta = –20 to 75°C) Parameter Enable cycle time Enable “H” level pulsewidth Enable rise/fall time RS, R/W setup time RS, R/W address hold time Read data setup time Read data hold time Symbol Rating Condition tcycE tWEH trE, tfE tAS tAH tRD tDHR CL = 100 pF Unit min max 500 — ns 220 — ns — 25 ns 40 — ns 10 — ns — 120 ns 20 — ns • External segment driver signal timing LP 0.9 VDD 0.9 VDD tWCLH tWCLH tDSLP XSCL 0.1 VDD 0.9 VDD 0.
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SED1278 • Power-on reset timing 4.5V 0.2V tr toff 0.1ms ≤ tr ≤ 10ms toff ≥ 1ms (Ta = –20 to 75 deg. C) LCD Drive Voltages Pin Duty 1/8 or 1/11 Duty 1/16 V1 3/4 (VDD – V5) 4/5 (VDD – V5) V2 2/4 (VDD – V5) 3/5 (VDD – V5) V3 2/4 (VDD – V5) 2/5 (VDD – V5) V4 1/4 (VDD – V5) 1/5 (VDD – V5) V5 V5 V5 Mechanical Specifications SED1278F Package Dimensions 0.992±0.016 (25.2±0.4) 0.787±0.004 (20.0±0.1) 64 41 Index 25 1 0.031±0.006 (0.8±0.15) SED1278 0.006±0.002 (0.15±0.05) 0.079±0.004 (2.
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SED1278 SED1278D Package Dimensions Chip size: 4.50 mm × 3.
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Pad X (µm) Y (µm) Pad X (µm) Y (µm) DB2 –2087 –1671 42 DB3 –1905 –1671 43 DB4 –1723 –1671 1671 44 DB5 –1541 –1671 1671 45 DB6 –1359 –1671 1177 1671 46 DB7 –1177 –1671 995 1671 47 COM1 –995 –1671 SEG15 814 1671 48 COM2 –814 –1671 SEG14 633 1671 49 COM3 –633 –1671 10 SEG13 452 1671 50 COM4 –452 –1671 11 SEG12 272 1671 51 COM5 –272 –1671 Number Name Number Name 1 SEG22 2087 1671 41 2 SEG21 1905 1671 3 SEG20 1723 1671 4 SEG19
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SED1278 OPERATION The Busy Flag System Initialization The SED1278 takes between 10 and 410 clock cycles to execute instructions. During that period additional instructions should not be issued. The device is provided with a busy flag to let the user check the internal state of the chip. BF should be 0 before another instruction is issued.
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SED1278 Software initialization Initialization during power-on reset involves several unstable factors related to power-supply output fluctuations. For this reason it is strongly recommended that a software initialization sequence is followed. • Software Initialization (8-bit MPU bus, fOSC = 250 kHz) Power-on [1] 30 ms or more [2] System set DB7 0 · · · · · · 0 1 1 * * * DB0 * RS 0 R/W 0 E DB0 * RS 0 R/W 0 E 4.
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SED1278 DB7 0 Display on/off [8] · · · · · · 0 0 1 0 0 DB0 0 RS 0 R/W 0 E 0 · · DB0 RS 0 R/W 0 E Display off Busy flag [9] BF=1 DB7 BF · · · · ACC BF=0 [10] Display Clear DB7 0 [11] Busy flag DB7 BF BF=1 · · · · · · 0 0 0 0 0 DB0 1 RS 0 R/W 0 E 0 · · · · · · DB0 RS 0 R/W 1 E 1 ACC BF=0 [12] Entry Mode set DB7 0 [13] Busy flag DB7 BF BF=1 · · · · · · 0 0 0 1 I/D DB0 S RS 0 R/W 0 E 0 · · · · · · DB0 RS 0 R/W 1
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SED1278 • Software Initialization (4-bit MPU bus, fOSC = 250 kHz) Power-on [1] 30 ms or more [2] System set DB7 0 · · 0 1 DB4 1 RS 0 R/W 0 E DB4 1 RS 0 R/W 0 E DB4 1 RS 0 R/W 0 E RS 0 R/W 0 E 4.
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SED1278 Display on/off [9] [10] Busy flag DB7 0 · · 0 0 DB4 0 (High-order) RS 0 R/W 0 1 0 0 0 (Low-order) 0 0 DB7 BF · · DB4 ACC (High-order) RS 0 R/W 1 E 1 ACC (Low-order) 0 1 1 E BF=1 E BF=0 [11] [12] DB7 0 · · 0 0 DB4 0 (High-order) RS 0 R/W 0 0 0 0 1 (Low-order) 0 0 DB7 BF · · DB4 ACC (High-order) RS 0 R/W 1 E 1 ACC (Low-order) 0 1 1 E Display clear Busy flag BF=1 BF=0 [13] [14] Entry Mode set DB7 0 · · 0 0 DB4 0 (High-o
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SED1278 THE CHARACTER GENERATOR Character Generator ROM (CGROM) Character Generator RAM (CGRAM) The SED1278 contains a 240 character, masked CGROM. Each character is 5×10 pixels, for 1/11 duty cycle compatibility. Refer to Appendix A for available codes and their corresponding fonts. Because the CGROM is masked, customers may arrange to have their own CGROM masks made. A custom mask allows the user to have • their own character set. • a character set of up to 256 characters.
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SED1278 5×11 pixel font (1/11 duty cycle) The maximum character height is 11 pixels, however if a cursor is used row 10 must be left blank. The SED1278 requires that, although the maximum character height is 11 rows, each character is allocated 16 rows (bytes) of address space. The last five bytes are ignored. The CGRAM address is made up of the following components. • The least significant 4 bits, a3 to a0, specify the row number of the character data.
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SED1278 LCD INTERFACE LCD Drive Voltages The SED1278 generates segment and common drive signals using the voltages supplied to pins V1, V2, V3, V4 and V5. The voltage levels at these pins depend on the duty cycle of the display. The specifications of these voltages. The simplest way of producing these voltages is to use a resistive dividing network. Figures 3 and 4 show examples of networks for 1/8, or 1/ 11, and 1/16 duty cycles respectively.
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SED1278 LCD Drive Signal Waveforms The segment and common drive waveforms generated by the SED1278, for various duty cycle ratios, are shown in figures 5, 6 and 7. tFR tFR .... VDD .... VSS FR .... .... .... .... VDD V1 V4 V5 COM 2 .... .... .... .... VDD V1 V4 V5 .... .... .... .... VDD V1 V4 V5 ······ COM 1 COM 8 .... VDD .... V2, V3 SEG 1 ....
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SED1278 tFR tFR .... VDD .... VSS FR .... .... .... .... VDD V1 V4 V5 COM 2 .... .... .... .... VDD V1 V4 V5 COM 16 .... .... .... .... VDD V1 V4 V5 SEG 1 .... VDD .... V5, V3 .... V5 ······ COM 1 Figure 7 1/16 Duty Cycle Drive Waveforms LCD Interface Configurations The SED1278 has 16 common and 40 segment drive outputs, enabling the chip to drive up to 16 characters by itself. The drive capability can be expanded to 80 characters, by using SED1181FLA external segment drivers.
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SED1278 • • • • • 1 line 8 characters 5×10 pixels + cursor 1/11 duty cycle System set: N = 0, F = 1 1 SED1278 · · · · · · · · · · · · · 8 ........ No. of characters ······· COM 1 COM 10 LCD panel COM 11 · · · · · · · · · · · · · ···· ···· SEG 1 SEG 40 • • • • • 1 line 20 characters 5×7 pixels + cursor 1/8 duty cycle System set: N = 0, F = 0 SED1278 1 · · · 9 8 · · · · · 20 ........ No.
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SED1278 • • • • • 1 line 80 characters 5×7 pixels + cursor 1/8 duty cycle System set: N = 0, F = 0 1 ........ 9 8 ........ 80 ........ No. of characters ........ COM 1 COM 7 COM8 LCD panel ... SEG 1 SEG40 SEG 0 .......SEG63 DO1 D0 DO0 SED1181FLA D1 XSCL LP FR DO .... .... .... (1) XSCL LP FR .......
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SED1278 • • • • • 2 line 20 characters 5×7 pixels + cursor 1/16 duty cycle System set: N = 1, F = don’t care SED1278 1 · · · 8 9 · · · · · 20 ........ No. of characters ···· COM1 1st line COM7 COM8 ···· COM9 2nd line COM15 COM16 LCD panel ·· ·· SEG 1 · · · · · · · · · NC SEG40 DO SEG0 D0 DO0 D1 · · · · · XSCL LP FR 9–28 EPSON SEG59 SEG60 XSCL LP ...
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SED1278 2 line 40 characters 5×7 pixels + cursor 16 duty cycle System set: N = 1, F = don‘t care 1 · · · · 9 8 · · · · · · · · · 40 ........ ···· SED1278 COM 1 No. of characters 1st line COM 7 COM 8 COM 9 ···· 2nd line COM15 COM16 ··· LCD panel SEG 1 ··· · · · · · · · · · SEG40 NC SEG 0 DO XSCL · · · SEG 0 ..SEG31 SEG32 SEG63 DO1 D0 DO0 LA D 1 SED1181F XSCL LP FR (1) ......
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SED1278 MPU INTERFACE The SED1278 has selectable 8- or 4-bit MPU interface. An example of a typical 8-bit MPU interface is shown figure 8.
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SED1278 COMPARISON WITH HD44780 BY HITACHI Item Data display RAM Character generator ROM Character font Character generator RAM LCD drive output Character font (with cursor) Conversion to duty LCD drive voltage (VDD–V5) LCD drive waveform E pulse width Timing to change the address counter subsequent to CGRAM and DDRAM data writing and reading HD44780 (Hitachi) SED1278 80 bytes ← 192 types 5 × 7: 160 types 5 × 10: 32 types 240 types 5 × 10: 240 types 64 bytes ← 16 common driver outputs 40 segment d
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SED1278 APPENDIX A: CHARACTER CODES AND FONTS SED1278F0A/SED1278D0A Higher 4-bit (D4 to D7) of Character Code (Hexadecimal) Lower 4-bit (D0 to D3) of Character Code (Hexadecimal) 0 9–32 0 CG RAM (1) 1 CG RAM (2) 2 CG RAM (3) 3 CG RAM (4) 4 CG RAM (5) 5 CG RAM (6) 6 CG RAM (7) 7 CG RAM (8) 8 CG RAM (1) 9 CG RAM (2) A CG RAM (3) B CG RAM (4) C CG RAM (5) D CG RAM (6) E CG RAM (7) F CG RAM (8) 1 2 3 4 5 6 7 EPSON 8 9 A B C D E F
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SED1278 SED1278F0B/SED1278D0B Higher 4-bit (D4 to D7) of Character Code (Hexadecimal) 0 1 CG RAM (2) 2 CG RAM (3) 3 CG RAM (4) 4 CG RAM (5) 5 CG RAM (6) 6 CG RAM (7) 7 CG RAM (8) 8 CG RAM (1) 9 CG RAM (2) A CG RAM (3) B CG RAM (4) C CG RAM (5) D CG RAM (6) E CG RAM (7) F CG RAM (8) 1 2 3 4 5 6 7 8 9 A B C D E F SED1278 Lower 4-bit (D0 to D3) of Character Code (Hexadecimal) 0 CG RAM (1) EPSON 9–33
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SED1278 SED1278F0C/SED1278D0C Higher 4-bit (D4 to D7) of Character Code (Hexadecimal) Lower 4-bit (D0 to D3) of Character Code (Hexadecimal) 0 9–34 0 CG RAM (1) 1 CG RAM (2) 2 CG RAM (3) 3 CG RAM (4) 4 CG RAM (5) 5 CG RAM (6) 6 CG RAM (7) 7 CG RAM (8) 8 CG RAM (1) 9 CG RAM (2) A CG RAM (3) B CG RAM (4) C CG RAM (5) D CG RAM (6) E CG RAM (7) F CG RAM (8) 1 2 3 4 5 6 7 EPSON 8 9 A B C D E F
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SED1278 SED1278F0E/SED1278D0E Higher 4-bit (D4 to D7) of Character Code (Hexadecimal) 0 1 CG RAM (2) 2 CG RAM (3) 3 CG RAM (4) 4 CG RAM (5) 5 CG RAM (6) 6 CG RAM (7) 7 CG RAM (8) 8 CG RAM (1) 9 CG RAM (2) A CG RAM (3) B CG RAM (4) C CG RAM (5) D CG RAM (6) E CG RAM (7) F CG RAM (8) 1 2 3 4 5 6 7 8 9 A B C D E F SED1278 Lower 4-bit (D0 to D3) of Character Code (Hexadecimal) 0 CG RAM (1) EPSON 9–35
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SED1278 SED1278F0G/SED1278D0G Higher 4-bit (D4 to D7) of Character Code (Hexadecimal) Lower 4-bit (D0 to D3) of Character Code (Hexadecimal) 0 9–36 0 CG RAM (1) 1 CG RAM (2) 2 CG RAM (3) 3 CG RAM (4) 4 CG RAM (5) 5 CG RAM (6) 6 CG RAM (7) 7 CG RAM (8) 8 CG RAM (1) 9 CG RAM (2) A CG RAM (3) B CG RAM (4) C CG RAM (5) D CG RAM (6) E CG RAM (7) F CG RAM (8) 1 2 3 4 5 6 7 EPSON 8 9 A B C D E F
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SED1278 SED1278F0H/SED1278D0H Higher 4-bit (D4 to D7) of Character Code (Hexadecimal) 0 CG RAM (1) 1 CG RAM (2) 2 CG RAM (3) 3 CG RAM (4) 4 CG RAM (5) 5 CG RAM (6) 6 CG RAM (7) 7 CG RAM (8) 8 CG RAM (1) 9 CG RAM (2) A CG RAM (3) B CG RAM (4) C CG RAM (5) D CG RAM (6) E CG RAM (7) F CG RAM (8) 1 2 3 4 5 6 7 8 9 A B C D E F SED1278 Lower 4-bit (D0 to D3) of Character Code (Hexadecimal) 0 EPSON 9–37
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SED1278 APPENDIX B: PIN CONSTRUCTION Input Pin Type 1 • E • OSC1 VDD VSS Input Pin Type 2 • RS • R/W VDD Pin VSS 9–38 EPSON
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SED1278 Output Pin • OSC2 • XSCL, LP, FR, DO VDD VSS I/O Pin • DB0 to DB7 VDD Pin SED1278 VSS EPSON 9–39