Specifications

S1D15300 Series
Rev.1.4 EPSON 5–35
(4) Display control timing
Notes: 1. The otput timing is valid in master mode.
2. Every timing is specified on the basis of 20% and 80% of V
DD
.
(5) Reset timing
Note: The reset timing is specified on the basis of 20% and 80% of V
DD.
Output timing V
DD
= 5.0 V ±10%, Ta = –40 to +85°C
Output timing V
SS
= 0 V, V
DD
= 2.7 V to 4.5 V, Ta = –40 to +85°C
Parameter Signal Symbol Condition Min. Typ. Max. Unit
FR delay time FR t
DFR
CL = 50 pF – 10 40 ns
DYO HIGH delay time DYO t
DOH
– 40 100 ns
DYO LOW delay time t
DOL
– 40 100 ns
Parameter Signal Symbol Condition Min. Typ. Max. Unit
FR delay time FR t
DFR
CL = 50 pF – 15 80 ns
DYO HIGH delay time DYO t
DOH
– 70 200 ns
DYO LOW delay time t
DOL
– 70 200 ns
Parameter Signal Symbol Condition Min. Typ. Max. Unit
Reset time
t
R
0.5 – – µs
Reset LOW pulse width RES t
RW
0.5 – – µs
V
DD
= 5.0 V ±10%, Ta = –40 to +85°C
V
DD
= 2.7 V to 4.5 V, Ta = –40 to +85°C
Parameter Signal Symbol Condition Min. Typ. Max. Unit
Reset time
t
R
1.0 – – µs
Reset LOW pulse width RES
t
RW
1.0 – – µs
CL
(OUT)
FR
t DFR
t DOH t DOL
DYO
t RW
t R
End of resetDuring reset
RES
Internal circuit
status