Specifications

S1D15300 Series
5–34 EPSON Rev.1.4
(3) Serial interface
Notes: 1. The input signal rise and fall times must be within 15 nanoseconds.
2. All signal timings are limited based on 20% and 80% of V
DD
voltage.
3. When it is expected that Vss ranges from -2.4 V to -4.5 V during the operation, increase all the above specifications from -2.7 V to
-4.5 V by 30% before the operation.
Parameter Signal Symbol Condition Min. Max. Unit
Serial clock cycle SCL
t
SCYC
250 – ns
Serial clock HIGH pulse width t
SHW
100 – ns
Serial clock LOW pulse width t
SLW
75 – ns
Address setup time A0
t
SAS
50 – ns
Address hold time
t
SAH
200 – ns
Data setup time SI
t
SDS
50 – ns
Data hold time
t
SDH
50 – ns
CS serial clock time CS
t
CSS
30 – ns
t
CSH
100 –
V
DD
= 5.0 V ±10%, Ta = –40 to +85°C
V
DD
= 2.7 to 4.5V, Ta = –40 to +85°C
Parameter Signal Symbol Condition Min. Max. Unit
Serial clock cycle SCL t
SCYC
500 – ns
Serial clock HIGH pulse width t
SHW
200 – ns
Serial clock LOW pulse width t
SLW
150 – ns
Address setup time A0
t
SAS
100 – ns
Address hold time
t
SAH
400 – ns
Data setup time SI
t
SDS
100 – ns
Data hold time
t
SDH
100 – ns
CS serial clock time CS
t
CSS
60 – ns
t
CSH
200 –
SCL
SI
A0
CS1
(CS2="1")
tSDS
tSHW
tSDH
tSLW
tSCYC
tSAS tSAH
tCSS tCSH
trtf