Specifications

S1D15300 Series
Rev.1.4 EPSON 5–33
(2) System buses
Read/write characteristics II (6800-series microprocessor)
Parameter Signal Symbol Condition Min. Max. Unit
System cycle time
t
CYC6
166 – ns
Address setup time A0
t
AW6
10 – ns
Address hold time W/R
t
AH6
10 – ns
Data setup time
t
DS6
20 – ns
Data hold time
D0 to D7
t
DH6
10 – ns
Output disable time
t
OH6
CL=100pF 10 50 ns
Access time
t
ACC6
–70ns
Enable READ
E
t
EWHR
70 – ns
LOW pulse width WRITE
t
EWHW
30 – ns
Enable READ
E
t
EWLR
70 – ns
HIGH pulse width WRITE
t
EWLW
100 – ns
V
DD
= 5.0 V ±10%, Ta = –40 to +85°C
V
DD
= 2.7 V to 4.5 V, Ta = –40 to +85°C
A0
CS1
(CS2="1")
E
D0~D7
(WR1TE)
D0~D7
(READ)
tAW6
tAH6
tEWHW tEWHR
tCYC6
tACC6
tOH6
tDS6
tEWLW tEWLR
tDH6
R/W
Notes: 1. The input rise/fall time (t
r
, t
f
) is specified at 15 ns or less. When the system cycle time is used at a high speed, it is specified by
t
r
+ t
f
≤ (t
CYC6
- t
EWLW
- t
EWHW
) or tr + tf ≤ (t
CYC6
- t
EWLR
- t
EWHR
).
2. Every timing is specified on the basis of 20% and 80% of V
DD
.
3. t
EWHR
and t
EWHW
are specified by the overlap period in which CS1 is “0” (CS2 = “1”) and E is “1”.
4. When it is expected that Vss ranges from -2.4 V to -4.5 V during the operation, increase all the above specifications from -2.7 V to
-4.5 V by 30% before the operation.
Parameter Signal Symbol Condition Min. Max. Unit
System cycle time
t
CYC6
450 – ns
Address setup time A0
t
AW6
15 – ns
Address hold time R/W
t
AH6
19 – ns
Data setup time
t
DS6
40 – ns
Data hold time
D0 to D7
t
DH6
15 – ns
Output disable time
t
OH6
CL=100pF 10 100 ns
Access time
t
ACC6
– 140 ns
Enable READ
E
t
EWHR
140 – ns
LOW pulse width WRITE
t
EWHW
60 – ns
Enable READ
E
t
EWLR
140 – ns
HIGH pulse width WRITE
t
EWLW
200 – ns