Specifications

S1D15300 Series
5–32 EPSON Rev.1.4
AC Characteristics
(1) System buses
Read/write characteristics I (8080-series microprocessor)
V
DD
= 5.0 V ±10%, Ta = –40 to +85°C
D0~D7
(READ)
D0~D7
(WRITE)
WR,RD
CS1
(CS2="1")
A0
tAW8 tAH8
tCYC8
tCCLW
tCCLR
tDS8 tDH8
tACC8 tCH8
tCCHW
tCCHR
Parameter Signal Symbol Condition Min. Max. Unit
Address hold time A0
t
AH8
19 – ns
Address setup time
t
AW8
15 – ns
System cycle time
t
CYC8
450 – ns
Control LOW pulse width (WR) WR
t
CCLW
60 – ns
Control LOW pulse width (RD) RD
t
CCLR
140 – ns
Control HIGH pulse width (WR) WR
t
CCHW
200 – ns
Control HIGH pulse width (RD) RD
t
CCHR
140 – ns
Data setup time
t
DS8
40 – ns
Data hold time
t
DH8
15 – ns
RD access time D0 to D7
t
ACC8
CL=100pF – 140 ns
Output disable time
t
CH8
10 100 ns
Parameter Signal Symbol Condition Min. Max. Unit
Address hold time A0
t
AHIGH8
10 – ns
Address setup time
t
AW8
10 – ns
System cycle time
t
CYC8
166 – ns
Control LOW pulse width(WR) WR
t
CCLOWW
30 – ns
Control LOW pulse width(RD) RD
t
CCLOWR
70 – ns
Control HIGH pulse width (WR) WR
t
CCHIGHW
100 – ns
Control HIGH pulse width (RD) RD
t
CCHIGHR
70 – ns
Data setup time
t
DS8
20 – ns
Data hold time
t
DHIGH8
10 – ns
RD access time D0 to D7
t
ACC8
CL=100pF – 70 ns
Output disable time
t
CHIGH8
10 50 ns
V
DD
= 2.7 V to 4.5 V, Ta = –40 to +85°C
Notes: 1. The input signal rise/fall time (t
r
, t
f
) is specified at 15 ns or less.
When system cycle time is used at a high speed, it is specified by t
r
+ t
f
≤ (t
CYC8
- t
CCLW
) or
t
r
+ t
f
≤ (t
CYC8
- t
CCLR
- t
CCHR
).
2. Every timing is specified on the basis of 20% and 80% of V
DD
.
3.
t
EWHR
and t
EWHW
are specified by the overlap period in which CS1 is “0” (CS2 = “1”) and WR and RD are “0”.
4. When it is expected that Vss ranges from -2.4 V to -4.5 V during the operation, increase all the above specifications from -2.7 V to
-4.5 V by 30% before the operation.