Specifications

S1D15300 Series
Rev.1.4 EPSON 5–19
(4) Set Column Address
Specifies column address of display RAM. Divide the column
address into 4 higher bits and 4 lower bits. Set each of them
succession. When the microprocessor repeats to access to the
display RAM, the column address counter is incremented by 1
during each access until address 132 is accessed. The page
address is not changed during this time.
(5) Read Status
BUSY: When high, the S1D15206 series is busy due to internal
operation or reset. Any command is rejected until BUSY
goes low. The busy check is not required if enough time
is provided for each cycle.
ADC: Indicates the relationship between RAM column address
and segment drivers. When low, the display is normal and
column address “131-n” corresponds to segment driver n.
When high, the display is reversed and column address n
corresponds to segment driver n.
ON/OFF: Indicates whether the display is on or off. When goes low,
the display turns on. When goes high, the display turns
off. This is the opposite of Display ON/OFF command.
RESET: Indicates the initialization is in progress by RES signal
or by Reset command. When low, the display is on.
When high, the chip is being reset.
(6) Write Display Data
Writes 8-bit data in display RAM. As the column address is
incremented by 1 automatically after each write, the microproc-
essor can continue to write data of multiple words.
7. COMMANDS
The S1D15300 series uses a combination of A0, RD (E) and WR (R/
W) signals to identify data bus signals. As the chip analyzes and
executes each command using internal timing clock only regardless
of external clock, its processing speed is very high and its busy check
is usually not required. The 8080 series microprocessor interface
enters a read status when a low pulse is input to the RD pin and a write
status when a low pulse is input to the WR pin. The 6800 series
microprocessor interface enters a read status when a high pulse is
input to the R/W pin and a write status when a low pulse is input to
this pin. When a high pulse is input to the E pin, the command is
activated. (For timing, see Timing Characteristics.) Accordingly, in
the command explanation and command table, RD (E) becomes 1
(high) when the 6800 series microprocessor interface reads status or
display data. This is an only different point from the 8080 series
microprocessor interface.
Taking the 8080 series microprocessor interface as an example,
commands will be explained below.
When the serial interface is selected, input data starting from D7 in
sequence.
(1) Display ON/OFF
Alternatively turns the display on and off.
The display turns off when D goes low, and it turns on when D
goes high.
(2) Start Display Line
Specifies line address (refer to Figure 4) to determine the initial
display line, or COM0. The RAM display data becomes the top
line of LCD screen. It is followed by the higher number of lines
in ascending order, corresponding to the duty cycle. When this
command changes the line address, the smooth scrolling or
page change takes place.
(3) Set Page Address
Specifies page address to load display RAM data to page
address register. Any RAM data bit can be accessed when its
page address and column address are specified. The display
remains unchanged even when the page address is changed.
Page address 8 is the display RAM area dedicate to the indica-
tor, and only D0 is valid for data change.
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0101010111D
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 0 1 A5A4A3A2A1A0
← High-order bit
A5 A4 A3 A2 A1 A0 Line address
000000 0
000001 1
000010 2
::
111110 6 2
111111 6 3
A3 A2 A1 A0 Page Address
0000 0
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
1000 8
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0101011A3A2A1A0
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Higher bits 0100001A7A6A5A4
Lower bits 0100000A3A2A1A0
A7 A6 A5 A4 A3 A2 A1 A0 Column address
00000000 0
00000001 1
::
10000011 1 3 1
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
001
BUSY ADC ON/OFF RESET 0000
E R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
1 1 0 Write data