Specifications
S1D15300 Series
5–12 EPSON Rev.1.4
Output Status Selector
The S1D15300 series except S1D15301 can set a COM output scan direction to reduce restrictions at LCD module assembly. This scan direction
is set by setting “1” or “0” in the output status register D3. Fig.5 shows the status.
Fig. 5 shows the status.
The COMS pin is assigned to COM32 on S1D15300 and it is assigned to COM64 on S1D15302 independent from their output status.
The COMS pin of the S1D15303 is assigned to COM16 the COMS pin of the S1D15304 is assigned to COM8 and the COMS pin of the S1D15305
is assigned to COM34.
Figure 5 shows the COM output pin numbers of S1D15302D00
**
and S1D15302D11
**
in the master mode. In the slave mode, COM0 to
COM31 must be replaced by COM32 to COM63.
Display Timing Generator
This section explains how the display timing generator circuit
operates.
Signal generation to line counter and display data latch
circuit
The display clock (CL) generates a clock to the line counter and a
latch signal to the display data latch circuit.
The line address of the display RAM is generated in synchronization
with the display clock. 132-bit display data is latched by the display
data latch circuit in synchronization with the display clock and
output to the segment LCD drive output pin.
The display data is read to the LCD drive circuit completely
independent of access to the display data RAM from the microproc-
essor.
LCD AC signal (FR) generation
The display clock generates an LCD AC signal (FR). The FR causes
the LCD drive circuit to generate a AC drive waveform.
It generates a 2-frame AC drive waveform.
When the S1D15300 is operated in slave mode on the assumption of
multi-chip, the FR pin and CL pin become input pins.
Common timing signal generation
The display clock generates an internal common timing signal and
a start signal (DYO) to the common driver. A display clock resulting
from frequency division of an oscillation clock is output from the CL
pin.
When an AC signal (FR) is switched, a high pulse is output as a DYO
output at the training edge of the previous display clock.
Refer to Fig. 6. The DYO output is output only in master mode.
When the S1D15300 series is used for multi-chip, the slave requires
to receive the FR, CL, DOF signals from the master.
Table 4 shows the FR, CL, DYO and DOF status.
Table 4
Column address
LCD output O0 O131
ADC
(D0)
"0"
"1"
0 (H)
83 (H)
83 (H)
0 (H)
D3
0
1
0
1
–
0
1
0
1
0
1
0
1
0
1
S1D15300D00
✽✽
S1D15300D10
✽✽
S1D15300D15
✽✽
S1D15301D00
✽✽
S1D15302D00
✽✽
S1D15302D14
✽✽
S1D15302D11
✽✽
S1D15303D15
✽✽
S1D15304D14
✽✽
S1D15305D10
✽✽
COM15 0
COM16 31
COM0
COM31
COM31
COM0
SEG100
SEG100
SEG100
SEG100
SEG132
SEG116
SEG116
SEG124
SEG124
SEG98
SEG98
COM16
COM15
31
0
COM8
COM7
COM0
COM7
COM18
COM17
15
0
7
0
33
0
Display data RAM
SEG100
SEG100
COM31
COM0
0
31
COM7
COM8
0
15
COM17
COM16
0
33
SEG100
SEG100
COM0
COM31
COM31
COM0
64 0 1 30 31 64 0
31
32
2
63
12
30
FR (master output)
Master Common
Slave Common
64 32 33 62 6334 64
Model
Operation
FR CL DYO DOF
mode
S1D1530
*
D
****
Master Output Output Output Output
Slave Input Input Hz Input
HZ denotes a high-impedance status.