Specifications

S1D15300 Series
5–8 EPSON Rev.1.4
6. FUNCTIONAL DESCRIPTION
Microprocessor Interface
Interface type selection
The S1D15300 series can transfer data via 8-bit bi-directional data buses (D7 to D0) or via serial data input (SI). When HIGH or LOW is selected
for the polarity of P/S pin, either 8-bit parallel data input or serial data input can be selected as shown in Table 1. When serial data input is selected,
RAM data cannot be read out.
Table 1
Parallel input
When the S1D15300 series selects parallel input (P/S = HIGH), the 8080 series microprocessor or 6800 series microprocessor can be selected
by causing the C86 pin to go HIGH or LOW as shown in Table 2.
Table 2
Data Bus Signals
The S1D15300 series identifies the data bus signal according to A0, E, R/W, (RD, WR) signals.
Table 3
Serial Interface (P/S is low)
The serial interface consists of an 8-bit shift register and a 3-bit counter. The serial data input and serial clock input are enabled when CS1 is
low and CS2 is high (in chip select status). When chip is not selected, the shift register and counter are reset.
Serial data of D7, D6, ..., D0 is read at D7 in this sequence when serial clock (SCL) goes high. They are converted into 8-bit parallel data and
processed on rising edge of every eighth serial clock signal.
The serial data input (S1) is determined to be the display data when A0 is high, and it is control data when A0 is low. A0 is read on rising edge
of every eighth clock signal.
Figure 1 shows a timing chart of serial interface signals. The serial clock signal must be terminated correctly against termination reflection and
ambient noise. Operation checkout on the actual machine is recommended.
P/S Type CS1 CS2 A0 RD WR C86 D7 D6 D0 to D5
HIGH Parallel input CS1 CS2 A0 RD WR C86 D7 D6 D0 to D5
LOW Serial input CS1 CS2 A0 – – – SI SCL (HZ)
“–” must always be HIGH or LOW.
Common 6800 processor 8080 processor
Function
A0 (R/W) RD WR
1 1 0 1 Reads display data.
1 0 1 0 Writes display data.
0 1 0 1 Reads status.
0 0 1 0 Writes control data in internal register. (Command)
C86 Type CS1 CS2 A0 RD WR D0 to D7
HIGH 6800 micro- CS1 CS2 A0 E R/W D0 to D7
processor bus
LOW 8080 micro- CS1 CS2 A0 RD RW D0 to D7
processor bus
CS1
SCL
1
A0
SI
CS2
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5
2345678910 1211
D4 D3 D2 D1
1413
Figure 1