Specifications

S1D15300 Series
Rev.1.4 EPSON 5–5
5. PIN DESCRIPTION
Power Supply
LCD Driver Supplies
Microprocessor Interface
Name I/O Description Number of pins
CAP1+ O DC/DC voltage converter capacitor 1 positive connection 1
CAP1– O DC/DC voltage converter capacitor 1 negative connection 1
CAP2+ O DC/DC voltage converter capacitor 2 positive connection 1
CAP2– O DC/DC voltage converter capacitor 2 negative connection 1
CAP3– O DC/DC voltage converter capacitor 1 negative connection 1
V
OUT
I/O DC/DC voltage converter output 1
VR I Voltage adjustment pin. Applies voltage between V
DD
and V5 using 1
a resistive divider.
Name I/O Description Number of pins
V
DD
Supply +5V power supply. Connect to microprocessor power supply pin V
CC
.2
V
SS
Supply Ground 1
V
1, V2 Supply LCD driver supply voltages. The voltage determined by LCD cell is
V
3, V4 impedance-converted by a resistive driver or an operational amplifier 6
V
5 for application. Voltages should be the following relationship:
V
DD
≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5
When the on-chip operating power circuit is on, the following voltages
are given to V
1
to V
4
by the on-chip power circuit. Voltage selection is
performed by the Set LCD Bias command. (The S1D15303 and S1D15304
are fixed to 1/5 bias.)
S1D15300/S1D15305 S1D15301 S1D15302
V
1 1/5•V5 1/6•V5 1/6•V5 1/8•V5 1/6•V5 1/8•V5
V2 2/5•V5 2/6•V5 2/6•V5 2/8•V5 2/6•V5 2/8•V5
V3 3/5•V5 4/6•V5 4/6•V5 6/8•V5 4/6•V5 6/8•V5
V4 4/5•V5 5/6•V5 5/6•V5 7/8•V5 5/6•V5 7/8•V5
S1D15303 S1D15304
V
1 1/5•V5 1/5•V5
V2 2/5•V5 2/5•V5
V3 3/5•V5 3/5•V5
V4 4/5•V5 4/5•V5
Name I/O Description Number of pins
D0 to D7 I/O 8-bit bi-directional data bus to be connected to the standard 8-bit or 16-bit 8
microprocessor data bus.
(SI) When the serial interface selects;
(SCL) D7: Serial data input (SI)
D6: Serial clock input (SCL)
A0 I Control/display data flag input. It is connected to the LSB of micro- 1
processor address bus. When LOW, the data on D0 to D7 is control data.
When HIGH, the data on D0 to D7 is display data.
RES When RES is caused to go LOW, initialization is executed. 1
A reset operation is performed at the RES signal level.
CS1 I Chip select input. Data input/output is enabled when -CS1 is LOW and 2
CS2 CS2 is HIGH. When chip select is non-active, D0 to D7 will be "HZ".
RD I • When interfacing to an 8080 series microprocessor: 1
(E) Active LOW. This input connects the RD signal of the 8080 series
microprocessor. While this signal is LOW, the S1D15300 series data
bus output is enabled.
• When interfacing to a 6800 series microprocessor:
Active HIGH. This is used as an enable clock input pin of the 6800 series
microprocessor.