Specifications

MODEL NO: 12232-10
PACIFIC DISPLAY DEVICES 04.25.2012 4
1.6 Input Signal Function
Pin No.
Symbol
Level
Description
Notes*
1
A0
H/L
H : Data signal, L : Instruction signal
2
/CS1
L
Chip select signal (Master Controller)
2
3
/CS2
L
Chip select signal (Slave Controller)
2
4
CL
H/L
2KHz External Clock (-FAA Chip Type)
5
5 /RD L
L : Read data bus from controller mode
Appropriate /CS line must also be active
This is the “R/W” line on the Graphic Controller
3, 4
6 /WR L
L : Write data bus to controller mode
Appropriate /CS line must also be active
This is theE” line on the Graphic Controller
3, 4
7
VSS
0V
Ground
8
DB0
H/L
Data bit 0
9
DB1
H/L
Data bit 1
19
DB2
H/L
Data bit 2
11
DB3
H/L
Data bit 3
12
DB4
H/L
Data bit 4
13
DB5
H/L
Data bit 5
14
DB6
H/L
Data bit 6
15
DB7
H/L
Data bit 7
16
VDD
5.0V
Supply voltage for logic
17 RES H L
Falling Edge Reset Selects 8080 Interface
Must be left “Low” during normal module operation
3
18
VO
---
Input voltage for LCD backplane (Contrast)
1
19
LED-A
4.2V
LED Backlight Anode
20
LED-K
0V
LED Backlight Cathode
*Notes:
1) VO is referenced to both VDD and temperature. See table on page 6 for exact value(s).
2) “/CS1” & /CS2tie to the separate /CS pins on the Master & Slave SED-1520 /
SBN1661G to be used as the
Controller select.
The “E” (/WR) line cannot be used as a “E” line in a 6800 implementation since it is common to both controllers.
3) This module can only use the 8080 style interface, and it is set by the state of the reset line.
Reset occurs when reset line transitions High to Low.
Reset line MUST be left in “Low” signal level condition during normal module operation
4) If /CS1 & /CS2 are both active (high), and /RD line is set to Read (low), damage can occur to module due to bus
contention causing serious over-current conditions.
5) External 2KHz clock must be supplied see SED-1520 /
SBN1661G data sheet for clock signal requirements
1.7 LCM Power, Contrast Control and Bias
VR:
20Kohm
Backlight
Power
VDD: +5V
VEE: -5.0V
VO
VSS
VDD
LED / EL
Backlight
A
K
LCM