Specifications

14 EPSON S1C6P466 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Address Comment
D3 D2
Register
D1 D0 Name Init
∗1
10
FF06H
FOUTE 0 FOFQ1 FOFQ0
R/W R R/W
FOUTE
0
∗ 3
FOFQ1
FOFQ0
0
–
∗ 2
0
0
Enable Disable
FOUT output enable
Unused
FOUT
frequency
selection
FF05H
00SVDDT SVDON
R R/W
0
∗ 3
0
∗ 3
SVDDT
SVDON
–
∗ 2
–
∗ 2
0
0
Low
On
Normal
Off
Unused
Unused
SVD evaluation data
SVD circuit On/Off
FF07H
00WDEN WDRST
R/W WR
0
∗ 3
0
∗ 3
WDEN
WDRST
∗ 3
–
∗ 2
–
∗ 2
1
Reset
Enable
Reset
Disable
Invalid
Unused
Unused
Watchdog timer enable
Watchdog timer reset (writing)
FF04H
SVDS3 SVDS2 SVDS1 SVDS0
R/W
SVDS3
SVDS2
SVDS1
SVDS0
0
0
0
0
SVD criteria voltage setting
FF00H
CLKCHG OSCC 0 VDC
R R/WR/W
CLKCHG
OSCC
0
∗ 3
VDC
0
0
–
∗ 2
0
OSC3
On
1
OSC1
Off
0
CPU clock switch
OSC3 oscillation On/Off
Unused
CPU operating voltage switch
FF20H
SIK03 SIK02 SIK01 SIK00
R/W
SIK03
SIK02
SIK01
SIK00
0
0
0
0
Enable
Enable
Enable
Enable
Disable
Disable
Disable
Disable
K00–K03 interrupt selection register
FF21H
K03 K02 K01 K00
R
K03
K02
K01
K00
–
∗ 2
–
∗ 2
–
∗ 2
–
∗ 2
High
High
High
High
Low
Low
Low
Low
K00–K03 input port data
FF22H
KCP03 KCP02 KCP01 KCP00
R/W
KCP03
KCP02
KCP01
KCP00
1
1
1
1
K00–K03 input comparison register
FF24H
SIK13 SIK12 SIK11 SIK10
R/W
SIK13
SIK12
SIK11
SIK10
0
0
0
0
Enable
Enable
Enable
Enable
Disable
Disable
Disable
Disable
K10–K13 interrupt selection register
FF25H
K13 K12 K11 K10
R
K13
K12
K11
K10
–
∗ 2
–
∗ 2
–
∗ 2
–
∗ 2
High
High
High
High
Low
Low
Low
Low
K10–K13 input port data
FF26H
KCP13 KCP12 KCP11 KCP10
R/W
KCP13
KCP12
KCP11
KCP10
1
1
1
1
K10–K13 input comparison register
0
1.05(Ext)
8
–
1
–
9
–
2
–
10
2.80
3
–
11
2.90
4
–
12
3.00
5
–
13
3.10
6
–
14
3.20
7
–
15
3.30
[SVDS3–0]
Voltage(V)
[SVDS3–0]
Voltage(V)
0
f
OSC1 /64
1
f OSC1 /8
2
f OSC1
3
f
OSC3
[FOFQ1, 0]
Frequency
FF30H
R03HIZ R02HIZ R01HIZ R00HIZ
R/W
R03HIZ
R02HIZ
R01HIZ
R00HIZ
0
0
0
0
High-Z
High-Z
High-Z
High-Z
Output
Output
Output
Output
R03 output high impedance control (FOUTE=0)
FOUT output high impedance control (FOUTE=1)
R02 output high impedance control (PTOUT=0)
TOUT output high impedance control (PTOUT=1)
R01 output high impedance control
R00 output high impedance control
FF31H
R03 R02 R01 R00
R/W
R03
R02
R01
R00
1
1
1
1
High
High
High
High
Low
Low
Low
Low
R03 output port data (FOUTE=0) Fix at "1" when FOUT is used
R02 output port data (PTOUT=0) Fix at "1" when TOUT is used
R01 output port data
R00 output port data
Table 4.1.1 (a) I/O memory map (FF00H–FF31H)
Remarks
∗1 Initial value at initial reset
∗2 Not set in the circuit
∗3 Constantly "0" when being read