Specifications

S1C6P466 TECHNICAL MANUAL EPSON 137
APPENDIX A PROM PROGRAMMING
Sample connection diagram for serial programming (S1C88/S1C63 Serial Connector)
SVD
CA
CB
CC
CD
CE
CF
OSC1
OSC2
OSC3
OSC4
V
SS
C 1
C 2
C 3
C 4
C 9
C GX
C DC
C P
+
X'tal
CR
K00–K03
K10–K13
P00–P03
P10 (SIN)
P11 (SOUT)
P12 (SCLK)
P13 (SRDY)
P20
P21
P22 (CL)
P23 (FR)
R00
R01
R02 (TOUT)
R03 (FOUT)
R10–R13
R20–R23
RSTOUT
VEPEXT
CLKIN
SCLK
RXD
TXD
RESET
SPRG
V
DDF
SEG0
|
SEG59
COM0
|
COM16
C
5
C
6
C
7
C
8
LCD panel 60 × 17
C GC
TEST
V
DD
V D1
V REF
V V V V V
C1 C2 C3 C4 C5
Input
I/O
Output
BZ
Piezo
Coil
External
voltage
Open
1 V DD
2 V DD
3 CLK
4 V
SS
5 SCLK
6 V
SS
7 RXD
8 V
SS
9 TXD
10 V
SS
11 RESET
12 V
SS
13 SPRG
14 V
SS
15 Reserved
16 Reserved
S1C88/S1C63
Serial Connector
Open
C RES
Exclusive cable
S1C6P466
[The potential of the substrate
(back of the chip) is V
SS .]
Note: The above table is sim
p
l
y
an exam
p
le, and is not
g
uaranteed to work.
X'tal
C
GX
CR
C
GC
C DC
C 1 –C 8
C 9
C P
C RES
Crystal oscillator
Trimmer capacitor
Ceramic oscillator
Gate capacitor
Drain capacitor
Capacitor
Capacitor
Capacitor
RESET terminal capacitor
32.768 kHz, C I (Max.) = 34 kΩ
5–25 pF
4 MHz
30 pF
30 pF
0.2 µF
0.1 µF
3.3 µF
0.1 µF
Fig. A.2.4.2 Sample connection diagram for serial programming (S1C88/S1C63 Serial Connector)
• In the serial programming mode, the power for the S1C6P466 is supplied from the VDD pin of the
S1C88/S1C63 Serial Connector.
• The operating clock (1 MHz) for serial programming is supplied from the CLK pin of the S1C88/
S1C63 Serial Connector to the S1C6P466.