Specifications

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MF1195

Technical Manual

CMOS 4

BIT SINGLE CHIP MICROCOMPUTER

S1C6P466 Technical Hardware

S1C6P466

Summary of content (175 pages)

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MF1195-03 CMOS 4-BIT SINGLE CHIP MICROCOMPUTER S1C6P466 Technical Manual S1C6P466 Technical Hardware
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NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.
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Revisions and Additions for this manual Chapter Appendix A Appendix B S1C6P466 Technical Manual Section A.2 Page 136 155 Item Contents Fig. A.2.4.1 Connection diagram for serial The diagram was revised. programming (S1C88/S1C63 Serial Connector) Table A.2.4.1 Signal specifications The table was revised. Appendix B Appendix B was added.
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The information of the product number change Starting April 1, 2001, the product number has been changed as listed below. Please use the new product number when you place an order. For further information, please contact Epson sales representative.
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CONTENTS CONTENTS CHAPTER 1 OUTLINE ________________________________________________ 1 1.1 1.2 1.3 1.4 1.5 CHAPTER Features ......................................................................................................... 1 Block Diagram .............................................................................................. 2 Pin Layout Diagram ..................................................................................... 3 Pin Description .........................................
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CONTENTS 4.5 Output Ports (R00–R03, R10–R13 and R20–R23) ...................................... 30 4.5.1 Configuration of output ports ................................................................... 30 4.5.2 Mask option ............................................................................................... 30 4.5.3 High impedance control ............................................................................ 31 4.5.4 Special output .........................................................
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CONTENTS 4.12 Sound Generator .......................................................................................... 79 4.12.1 Configuration of sound generator .......................................................... 79 4.12.2 Mask option ............................................................................................. 79 4.12.3 Control of buzzer output .......................................................................... 79 4.12.4 Setting of buzzer frequency and sound level ........
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CONTENTS CHAPTER 9 ELECTRICAL CHARACTERISTICS _______________________________ 113 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 CHAPTER Absolute Maximum Rating .......................................................................... 113 Recommended Operating Conditions ......................................................... 113 DC Characteristics ..................................................................................... 114 Analog Circuit Characteristics and Power Current Consumption ............
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CHAPTER 1: OUTLINE CHAPTER 1 OUTLINE The S1C6P466 is a microcomputer which has a high-performance 4-bit CPU S1C63000 as the core CPU, rewritable Flash EEPROM (hereinafter called PROM), RAM, dot-matrix LCD driver, serial interface and timers. The S1C6P466 has a built-in large capacity PROM (16K × 13 bits) and RAM (5K × 4 bits) that are compatible with the S1C63454, S1C63458 and S1C63466, it can therefore be used as an MTP (MultiTime Programming) for program development. 1.
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CHAPTER 1: OUTLINE 1.
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CHAPTER 1: OUTLINE 1.3 Pin Layout Diagram QFP8-144pin (Note) QFP17-144pin 108 108 73 72 109 72 109 73 S1C6P466 S1C6P466 INDEX INDEX 37 144 1 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 S1C63458 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM7 COM6 COM5 COM4 N.C. COM3 COM2 COM1 COM0 BZ VSS OSC1 OSC2 VD1 OSC3 OSC4 VDD RESET TEST VREF N.C. N.C.
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CHAPTER 1: OUTLINE 1.4 Pin Description Table 1.4.1 Pin description Pin name VDD VSS VD1 VC1–VC5 VREF CA–CF OSC1 OSC2 OSC3 OSC4 K00–K03 K10, K11 K12 K13 P00–P03 P10–P13 P20 P21 P22 P23 R00 R01 R02 R03 R10–R13 R20–R23 COM0, COM1 COM2–COM14 COM15, COM16 SEG0–SEG59 BZ SVD RESET TEST TXD RXD SCLK CLKIN SPRG RSTOUT VDDF VEPEXT 4 Pin No.
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CHAPTER 1: OUTLINE 1.5 Mask Option The mask options provided for the S1C63454/63458/63466 are fixed as follows in the S1C6P466, so they cannot be selected. Table 1.5.1 S1C6P466 mask option configuration Mask option Setting OSC1 oscillation circuit Crystal oscillation (32.
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CHAPTER 2: POWER SUPPLY AND INITIAL RESET CHAPTER 2 POWER SUPPLY AND INITIAL RESET 2.1 Power Supply The S1C6P466 operating power voltage is as follows: Table 2.1.1 Operating power voltage Operating mode MCU normal operation mode PROM programming mode Operating power voltage 2.7 V–5.5 V 5.0 V ±10% The S1C6P466 operates by applying a single power supply within the above range between VDD/VDDF and VSS.
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CHAPTER 2: POWER SUPPLY AND INITIAL RESET 2.1.1 Voltage for oscillation circuit VD1 is the operating voltage for the oscillation circuit, and is generated by the oscillation system voltage regulator for stabilizing the oscillation. In the S1C63454/63458/63466, it is necessary to switch the VD1 voltage level according to the oscillation circuit and operating frequency by controlling the voltage regulator.
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CHAPTER 2: POWER SUPPLY AND INITIAL RESET 2.2 Initial Reset To initialize the S1C6P466 circuits, initial reset must be executed. The S1C6P466 supports the initial reset factor below. External initial reset by the RESET terminal When the power is turned on, be sure to initialize using the reset function. It is not guaranteed that the circuits are initialized by only turning the power on. Figure 2.2.1 shows the configuration of the initial reset circuit.
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CHAPTER 2: POWER SUPPLY AND INITIAL RESET If an instruction which does not permit extended operation is used as the following instruction, the operation is not guaranteed. Therefore, do not write data to the EXT register for initialization only. Refer to the "S1C63000 Core CPU Manual" for extended addressing and usable instructions. Table 2.2.2.
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CHAPTER 2: POWER SUPPLY AND INITIAL RESET 2.3 Test Terminal (TEST) This is the terminal used for the factory inspection of the IC. During normal operation, connect the TEST terminal to VDD. 2.4 Terminals for Flash EEPROM The S1C6P466 has the following terminals used for writing data to the Flash EEPROM and for factory testing.
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CHAPTER 3: CPU, PROM, RAM CHAPTER 3 CPU, PROM, RAM 3.1 CPU The S1C6P466 has a 4-bit core CPU S1C63000 built-in as its CPU part. Refer to the "S1C63000 Core CPU Manual" for the S1C63000. Note: The SLP instruction cannot be used because the SLEEP operation is not assumed in the S1C6P466. 3.2 Code PROM The built-in code PROM is a PROM for loading programs, and has a capacity of 16,384 steps × 13 bits.
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CHAPTER 3: CPU, PROM, RAM (3) Subroutine calls use 4 words (for PC evacuation) in the stack area for 16-bit data (SP1). Interrupts use 4 words (for PC evacuation) in the stack area for 16-bit data (SP1) and 1 word (for F register evacuation) in the stack area for 4-bit data. 0000H 4-bit access area (SP2 stack area) 00FFH 0100H 4/16-bit access area (SP1 stack area) 01FFH 0200H 4-bit access area (Data area) 13FFH 4 bits Fig. 3.3.1 Configuration of data RAM 3.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION The peripheral circuits of S1C6P466 (timer, I/O, etc.) are interfaced with the CPU in the memory mapped I/O method. Thus, all the peripheral circuits can be controlled by accessing the I/O memory on the memory map using the memory operation instructions. The following sections explain the detailed operation of each peripheral circuit. 4.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Watchdog Timer) 4.2 Watchdog Timer 4.2.1 Configuration of watchdog timer The S1C6P466 has a built-in watchdog timer that operates with a 256 Hz divided clock from the OSC1 as the source clock. The watchdog timer starts operating after initial reset, however, it can be stopped by the software. The watchdog timer must be reset cyclically by the software while it operates.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Watchdog Timer) 4.2.3 I/O memory of watchdog timer Table 4.2.3.1 shows the I/O address and control bits for the watchdog timer. Table 4.2.3.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) 4.3 Oscillation Circuit 4.3.1 Configuration of oscillation circuit The S1C6P466 has two oscillation circuits (OSC1 and OSC3). OSC1 is a crystal oscillation circuit that supplies the operating clock to the CPU and peripheral circuits. OSC3 is a ceramic oscillation circuit. When processing with the S1C6P466 requires high-speed operation, the CPU operating clock can be switched from OSC1 to OSC3 by software. Figure 4.3.1.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) As shown in Figure 4.3.3.1, the ceramic oscillation circuit can be configured by connecting the ceramic oscillator (Max. 4 MHz) between the OSC3 and OSC4 terminals, capacitor CGC between the OSC3 and OSC4 terminals, and capacitor CDC between the OSC4 and VSS terminals. For both CGC and CDC, connect capacitors that are about 30 pF.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) 4.3.7 I/O memory of oscillation circuit Table 4.3.7.1 shows the I/O address and the control bits for the oscillation circuit. Table 4.3.7.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) 4.3.8 Programming notes (1) It takes at least 5 msec from the time the OSC3 oscillation circuit goes ON until the oscillation stabilizes. Consequently, when switching the CPU operation clock from OSC1 to OSC3, do this after a minimum of 5 msec have elapsed since the OSC3 oscillation went ON.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) 4.4 Input Ports (K00–K03 and K10–K13) 4.4.1 Configuration of input ports The S1C6P466 has eight bits of general-purpose input ports. Each of the input port terminals (K00–K03, K10–K13) provides a pull-up resistor. Figure 4.4.1.1 shows the configuration of the input port. Interrupt request Kxx Data bus VDD Address VSS Fig. 4.4.1.1 Configuration of input port 4.4.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) The interrupt selection register (SIK) and input comparison register (KCP) are individually set for the input ports K00–K03 and K10–K13, and can specify the terminals for generating interrupt and interrupt timing. The interrupt selection registers (SIK00–SIK03, SIK10–SIK13) select what input of K00–K03 and K10–K13 to use for the interrupt.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) 4.4.4 I/O memory of input ports Table 4.4.4.1 shows the I/O addresses and the control bits for the input ports. Table 4.4.4.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) SIK00–SIK03: K0 port interrupt selection register (FF20H) SIK10–SIK13: K1 port interrupt selection register (FF24H) Selects the ports to be used for the K00–K03 and K10–K13 input interrupts. When "1" is written: Enable When "0" is written: Disable Reading: Valid Enables the interrupt for the input ports (K00–K03, K10–K13) for which "1" has been written into the interrupt selection registers (SIK00–SIK03, SIK10–SIK13).
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) 4.4.5 Programming notes (1) When input ports are changed from low to high by pull-up resistors, the rise of the waveform is delayed on account of the time constant of the pull-up resistor and input gate capacitance. Hence, when fetching input ports, set an appropriate waiting time. Particular care needs to be taken of the key scan during key matrix configuration.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) 4.5 Output Ports (R00–R03, R10–R13 and R20–R23) 4.5.1 Configuration of output ports The S1C6P466 has 12 bits of general output ports. The output specification of each output port is fixed at complementary output. Figure 4.5.1.1 shows the configuration of the output port. Data bus Address VDD High impedance control register Data register Rxx Address VSS Fig. 4.5.1.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) 4.5.3 High impedance control The terminal output status of the output ports can be set to a high impedance status. This control is done using the high impedance control registers. The high impedance control registers are provided to correspond with the output ports as shown below.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) • TOUT (R02) The R02 terminal can output a TOUT signal. The TOUT signal is the clock that is output from the programmable timer, and can be used to provide a clock signal to an external device. To output the TOUT signal, fix the R02 register at "1" and the R02HIZ register at "0", and turn the signal ON and OFF using the PTOUT register. It is, however, necessary to control the programmable timer. Refer to Section 4.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) 4.5.5 I/O memory of output ports Table 4.5.5.1 shows the I/O addresses and control bits for the output ports. Table 4.5.5.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) R00–R03: R0 output port data register (FF31H) R10–R13: R1 output port data register (FF33H) R20–R23: R2 output port data register (FF35H) Set the output data for the output ports. When "1" is written: High level output When "0" is written: Low level output Reading: Valid The output port terminals output the data written in the corresponding data registers without changing it.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) 4.5.6 Programming notes (1) When using the output port (R02, R03) as the special output port, fix the data register (R02, R03) at "1" and the high impedance control register (R02HIZ, R03HIZ) at "0" (data output). Be aware that the output terminal is fixed at a low (VSS) level the same as the DC output if "0" is written to the R02 and R03 registers when the special output has been selected.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) 4.6 I/O Ports (P00–P03, P10–P13 and P20–P23) 4.6.1 Configuration of I/O ports The S1C6P466 has 12 bits of general-purpose I/O ports. Figure 4.6.1.1 shows the configuration of the I/O port. Data bus Address VDD Pull-up control register (PUL) Address Address Data register Address I/O control register (IOC) PXX Fig. 4.6.1.1 Configuration of I/O port The I/O port terminals P10 to P13 are shared with the serial interface input/output terminals.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) 4.6.3 I/O control registers and input/output mode Input or output mode can be set for the I/O ports by writing data into the corresponding I/O control registers IOCxx. To set the input mode, write "0" to the I/O control register. When an I/O port is set to input mode, it becomes high impedance status and works as an input port.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) 4.6.5 Special outputs (CL, FR) The I/O ports P22 and P23 can be used as special output ports that output CL and FR signals by switching the function with software. Since P22 and P23 are set to I/O port (input mode) at initial reset, when using the special outputs, select the special output function using the EXLCDC register.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) 4.6.6 I/O memory of I/O ports Tables 4.6.6.1(a) and (b) show the I/O addresses and the control bits for the I/O ports. Table 4.6.6.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) Table 4.6.6.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) (2) I/O port control P00–P03: P0 I/O port data register (FF42H) P10–P13: P1 I/O port data register (FF46H) P20–P23: P2 I/O port data register (FF4AH) I/O port data can be read and output data can be set through these registers. • When writing data When "1" is written: High level When "0" is written: Low level When an I/O port is set to the output mode, the written data is output unchanged from the I/O port terminal.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) PUL00–PUL03: P0 port pull-up control register (FF41H) PUL10–PUL13: P1 port pull-up control register (FF45H) PUL20–PUL23: P2 port pull-up control register (FF49H) The pull-up during the input mode are set with these registers. When "1" is written: Pull-up ON When "0" is written: Pull-up OFF Reading: Valid The built-in pull-up resistor which is turned ON during input mode is set to enable in 1-bit units.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) 4.7 LCD Driver (COM0–COM16, SEG0–SEG59) 4.7.1 Configuration of LCD driver The S1C6P466 has 17 common terminals (COM0–COM16) and 60 segment terminals (SEG0–SEG59), so that it can drive a dot matrix type LCD with a maximum of 1,020 (60 × 17) dots. The driving method is 1/17 duty, 1/16 duty or 1/8 duty dynamic drive with four voltages (1/4 bias), VC1, VC2, VC4 and VC5. LCD display can be controlled by the software. 4.7.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) 4.7.4 LCD display control (ON/OFF) and switching of duty (1) Display ON/OFF control The S1C6P466 incorporates the ALON and ALOFF registers to blink display. When "1" is written to ALON, all the dots go ON, and when "1" is written to ALOFF, all the dots go OFF. At such a time, an ON waveform or an OFF waveform is output from SEG terminals. When "0" is written to these registers, normal display is performed.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) Drive duty 1/8 1/16 0 1 2 3 0 1 2 3 ..... ..... 7 0 1 2 3 15 0 1 2 3 ..... ..... 7 15 1/17 0 1 2 3 ..... 16 0 1 2 3 ..... 16 (LPAGE = 0) Frame signal 32 Hz ∗ ∗ When fOSC1 = 32.768 kHz VC5 VC4 VC2 (VC3) VC1 VSS COM0 VC5 VC4 VC2 (VC3) VC1 COM1 VSS COM2 VC5 VC4 VC2 (VC3) VC1 VSS SEG0 VC5 VC4 VC2 (VC3) VC1 VSS VC5 VC4 VC2 (VC3) VC1 VSS SEG1 Fig. 4.7.4.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) 4.7.5 Display memory 1/16 duty 1/17 duty The display memory is allocated to F000H–F276H in the data memory area and the addresses and the data bits correspond to COM and SEG outputs as shown in Figure 4.7.5.1. COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SEG0 ■ D0 ■ D1 F000H ■ D2 ■ D3 ■ D0 ■ D1 F001H ■ D2 ■ D3 SEG1 ■ D0 ■ D1 F002H ■ D2 ■ D3 ■ D0 ■ D1 F003H ■ D2 ■ D3 SEG2 ■ D0 ■ D1 F004H ■ D2 ■ D3 ■ D0 ■ D1 F005H ■ D2 ■ D3 SEG3 ■ D0 ■ D1 F006H . .
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) When a bit in the display memory is set to "1", the corresponding LCD dot goes ON, and when it is set to "0", the dot goes OFF. At 1/17 (1/16) duty drive, all data of COM0–COM16 (15) is output. At 1/8 duty drive, data only corresponding to COM0–COM7 is output. However, since the display memory has capacity for two screens, it is designed so that the memory for COM8–COM15 shown in Figure 4.7.5.1 (b) can also be used as COM0–COM7.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) 4.7.7 I/O memory of LCD driver Table 4.7.7.1 shows the I/O addresses and the control bits for the LCD driver. Figure 4.7.7.1 shows the display memory map. Table 4.7.7.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) VCCHG: LCD regulated voltage switching register (FF60H•D1) Selects the reference voltage for the LCD drive voltage. When "1" is written: VC2 When "0" is written: VC1 Reading: Valid When "1" is written to the VCCHG register, the LCD system voltage circuit generates the LCD drive voltage as VC2 standard. When "0" is written, it becomes VC1 standard.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) LPAGE: LCD display memory selection register (FF61H•D0) Selects the display memory area at 1/8 duty drive. When "1" is written: F100H–F177H When "0" is written: F000H–F077H Reading: Valid By writing "1" to the LPAGE register, the data set in F100H–F177H (the second half of the display memory) is displayed, and when "0" is written, the data set in F000H–F077H (the first half of the display memory) is displayed.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) 4.8 Clock Timer 4.8.1 Configuration of clock timer The S1C6P466 has a built-in clock timer that uses OSC1 (crystal oscillator) as the source oscillator. The clock timer is configured of an 8-bit binary counter that serves as the input clock, fOSC1 divided clock output from the prescaler. Timer data (128–16 Hz and 8–1 Hz) can be read out by the software. Figure 4.8.1.1 is the block diagram for the clock timer.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) 4.8.3 Interrupt function The clock timer can cause interrupts at the falling edge of 32 Hz, 8 Hz, 2 Hz and 1 Hz signals. Software can set whether to mask any of these frequencies. Figure 4.8.3.1 is the timing chart of the clock timer.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) 4.8.4 I/O memory of clock timer Table 4.8.4.1 shows the I/O addresses and the control bits for the clock timer. Table 4.8.4.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) EIT0: 32 Hz interrupt mask register (FFE6H•D0) EIT1: 8 Hz interrupt mask register (FFE6H•D1) EIT2: 2 Hz interrupt mask register (FFE6H•D2) EIT3: 1 Hz interrupt mask register (FFE6H•D3) These registers are used to select whether to mask the clock timer interrupt.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer) 4.9 Stopwatch Timer 4.9.1 Configuration of stopwatch timer The S1C6P466 has 1/100 sec unit and 1/10 sec unit stopwatch timer built-in. The stopwatch timer is configured with a 2 levels 4-bit BCD counter which has an input clock approximating 100 Hz signal (signal divided from OSC1 to the closest 100 Hz) and data can be read in units of 4 bits by software. Figure 4.9.1.1 shows the configuration of the stopwatch timer.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer) SWD0–SWD3 generates an approximated 10 Hz signal from the basic 256 Hz signal (fOSC1 dividing clock). The count-up intervals are 2/256 sec and 3/256 sec, so that finally two patterns are generated: 25/ 256 sec and 26/256 sec intervals. Consequently, these patterns do not amount to an accurate 1/100 sec.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer) 4.9.4 I/O memory of stopwatch timer Table 4.9.4.1 shows the I/O addresses and the control bits for the stopwatch timer. Table 4.9.4.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer) When data of the counter is read at run mode, proper reading may not be obtained due to the carry from low-order digits (SWD0–SWD3) into high-order digits (SWD4–SWD7) (i.e., in case SWD0–SWD3 and SWD4–SWD7 reading span the timing of the carry). To avoid this occurrence, perform the reading after suspending the counter once and then set the SWRUN to "1" again.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer) 4.10 Programmable Timer 4.10.1 Configuration of programmable timer The S1C6P466 has two 8-bit programmable timer systems (timer 0 and timer 1) built-in. Timer 0 and timer 1 are composed of 8-bit presettable down counters and they can be used as 8-bit × 2 channel programmable timers. Timer 0 also has an event counter function using the K13 input port terminal. Figure 4.10.1.1 shows the configuration of the programmable timer.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer) 4.10.2 Setting of initial value and counting down Timers 0 and 1 each have a down counter and reload data register. The reload data registers RLD00–RLD07 (timer 0) and RLD10–RLD17 (timer 1) are used to set the initial value to the down counter. By writing "1" to the timer reset bit PTRST0 (timer 0) or PTRST1 (timer 1), the down counter loads the initial value set in the reload register RLD.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer) 4.10.3 Counter mode The programmable timer can operate in two counter modes, timer mode and event counter mode. It can be selected by software. (1) Timer mode The timer mode counts down using the prescaler output as an input clock. In this mode, the programmable timer operates as a periodical timer using the OSC1 or OSC3 oscillation clock as a clock source. Timer 0 can operate in both the timer mode and the event counter mode.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer) 2,048 Hz ∗1 K13 input Counter input clock ∗2 Counter data n n-1 n-2 n-3 ∗1 When fOSC1 is 32.768 kHz ∗2 When PLPOL register is set to "0" Fig. 4.10.3.2 Count down timing with noise rejecter The operation of the event counter mode is the same as the timer mode except it uses the K13 input as the clock. Refer to Section 4.10.2, "Setting of initial value and counting down" for basic operation and control. 4.10.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer) 4.10.5 Interrupt function The programmable timer can generate an interrupt due to an underflow of the timer 0 and timer 1. See Figure 4.10.2.1 for the interrupt timing. An underflow of timer 0 and timer 1 sets the corresponding interrupt factor flag IPT0 (timer 0) or IPT1 (timer 1) to "1", and generates an interrupt. The interrupt can also be masked by setting the corresponding interrupt mask register EIPT0 (timer 0) or EIPT1 (timer 1).
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer) 4.10.7 Transfer rate setting for serial interface The signal that is made from underflows of timer 1 by dividing them in 1/2, can be used as the clock source for the serial interface. The programmable timer outputs the clock to the serial interface by setting timer 1 into RUN state (PTRUN = "1"). It is not necessary to control with the PTOUT register. PTRUN1 Timer 1 underflow Source clock for serial I/F Fig. 4.10.7.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer) 4.10.8 I/O memory of programmable timer Table 4.10.8.1 shows the I/O addresses and the control bits for the programmable timer. Table 4.10.8.1 Control bits of programmable timer Address FFC0H FFC1H FFC2H FFC3H FFC4H FFC5H FFC6H FFC7H FFC8H FFC9H FFCAH FFCBH FFE2H FFF2H Register Name Init ∗1 1 0 ∗3 – ∗2 0 EVCNT FCSEL PLPOL EVCNT 0 Event ct.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer) CKSEL0: Prescaler 0 source clock selection register (FFC1H•D0) CKSEL1: Prescaler 1 source clock selection register (FFC1H•D1) Selects the source clock of the prescaler. When "1" is written: OSC3 clock When "0" is written: OSC1 clock Reading: Valid The source clock for the prescaler is selected from OSC1 or OSC3.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer) FCSEL: Timer 0 function selection register (FFC0H•D1) Selects whether the noise rejector of the clock input circuit will be used or not in the event counter mode. When "1" is written: With noise rejecter When "0" is written: Without noise rejecter Reading: Valid When "1" is written to the FCSEL register, the noise rejecter is used and counting is done by an external clock (K13) with 0.98 msec* or more pulse width.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer) PTRST0: Timer 0 reset (reload) (FFC2H•D1) PTRST1: Timer 1 reset (reload) (FFC3H•D1) Resets the timer and presets reload data to the counter. When "1" is written: Reset When "0" is written: No operation Reading: Always "0" By writing "1" to PTRST0, the reload data in the reload register PLD00–PLD07 is preset to the counter in timer 0. Similarly, the reload data in PLD10–PLD17 is preset to the counter in timer 1 by PTRST1.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer) EIPT0: Timer 0 interrupt mask register (FFE2H•D0) EIPT1: Timer 1 interrupt mask register (FFE2H•D1) These registers are used to select whether to mask the programmable timer interrupt or not. When "1" is written: Enabled When "0" is written: Masked Reading: Valid Timer 0 and timer 1 interrupts can be masked individually by the interrupt mask registers EIPT0 (timer 0) and EIPT1 (timer 1). At initial reset, these registers are set to "0".
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer) 4.10.9 Programming notes (1) When reading counter data, be sure to read the low-order 4 bits (PTD00–PTD03, PTD10–PTD13) first. Furthermore, the high-order 4 bits (PTD04–PTD07, PTD14–PTD17) should be read within 0.73 msec (when fOSC1 is 32.768 kHz) of reading the low-order 4 bits (PTD00–PTD03, PTD10–PTD13).
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) 4.11 Serial Interface (SIN, SOUT, SCLK, SRDY) 4.11.1 Configuration of serial interface The S1C6P466 has a synchronous clock type 8-bit serial interface built-in. The configuration of the serial interface is shown in Figure 4.11.1.1. The CPU, via the 8-bit shift register, can read the serial input data from the SIN terminal.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) 4.11.2 Mask option (1) Terminal specification Since the input/output terminals of the serial interface is shared with the I/O ports (P10–P13), the terminal specification of the I/O port is also applied to the serial interface. In the S1C6P466, the I/O port specification is fixed at "with pull-up resistor" and "complementary output".
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) S1C6P466 External serial device S1C6P466 External serial device SCLK CLK SCLK CLK SOUT SOUT SOUT SOUT SIN SIN SIN Input terminal SIN SRDY READY (a) Master mode Input terminal (b) Slave mode Fig. 4.11.3.1 Sample basic connection of serial input/output section 4.11.4 Data input/output and interrupt function The serial interface of S1C6P466 can input/output data via the internal 8-bit shift register.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) (3) Serial data input/output permutation The S1C6P466 allows the input/output permutation of serial data to be selected by the SDP register (FF71H•D3) as to either LSB first or MSB first. The block diagram showing input/output permutation in case of LSB first and MSB first is provided in Figure 4.11.4.1. The SDP register should be set before setting data to SD0–SD7.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) 4.11.5 I/O memory of serial interface Table 4.11.5.1 shows the I/O addresses and the control bits for the serial interface. Table 4.11.5.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) PUL10: SIN (P10) pull-up control register (FF45H•D0) PUL12: SCLK (P12) pull-up control register (FF45H•D2) Sets the pull-up of the SIN terminal and the SCLK terminals (in the slave mode). When "1" is written: Pull-up ON When "0" is written: Pull-up OFF Reading: Valid Sets the pull-up resistor built into the SIN (P10) and SCLK (P12) terminals to ON or OFF. SCLK pull-up is effective only in the slave mode.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) SCTRG: Clock trigger/status (FF70H•D1) This is a trigger to start input/output of synchronous clock (SCLK). • When writing When "1" is written: Trigger When "0" is written: No operation When this trigger is supplied to the serial interface activating circuit, the synchronous clock (SCLK) input/output is started.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) ISIF: Interrupt factor flag (FFF3H•D0) This flag indicates the occurrence of serial interface interrupt. When "1" is read: Interrupt has occurred When "0" is read: Interrupt has not occurred When "1" is written: Flag is reset When "0" is written: Invalid From the status of this flag, the software can decide whether the serial interface interrupt. This flag is set to "1" after an 8-bit data input/output even if the interrupt is masked.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator) 4.12 Sound Generator 4.12.1 Configuration of sound generator The S1C6P466 has a built-in sound generator for generating buzzer signals. Hence, generated buzzer signals (BZ) can be output from the BZ terminal. Aside permitting the respective setting of the buzzer signal frequency and sound level to 8 stages, it permits the adding of a digital envelope by means of duty ratio control.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator) 4.12.4 Setting of buzzer frequency and sound level The divided signal of the OSC1 oscillation clock (32.768 kHz) is used for the buzzer (BZ) signal and it is set up such that 8 types of frequencies can be selected by changing this division ratio. Frequency selection is done by setting the buzzer frequency selection registers BZFQ0–BZFQ2 as shown in Table 4.12.4.1. Table 4.12.4.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator) 4.12.5 Digital envelope A digital envelope for duty control can be added to the buzzer signal. The envelope can be controlled by staged changing of the same duty envelope as detailed in Table 4.12.4.2 in the preceding item from level 1 (maximum) to level 8 (minimum). The addition of an envelope to the buzzer signal can be done by writing "1" into ENON, but when "0" has been written it is not added.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator) 4.12.6 One-shot output The sound generator has a one-shot output function for outputting a short duration buzzer signal for key operation sounds and similar effects. Either 125 msec or 31.25 msec can be selected by SHTPW register for one-shot buzzer signal output time. The output of the one-shot buzzer is controlled by writing "1" into the one-shot buzzer trigger BZSHT.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator) 4.12.7 I/O memory of sound generator Table 4.12.7.1 shows the I/O addresses and the control bits for the sound generator. Table 4.12.7.1 Control bits of sound generator Address Register D3 D2 ENRTM ENRST FF6CH R/W W 0 BZSTP R W 0 BZFQ2 FF6DH FF6EH R 0 FF6FH R BDTY2 Name Init ∗1 1 0 ENRTM 0 1 sec 0.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator) BDTY0–BDTY2: Duty level selection register (FF6FH•D0–D2) Selects the duty ratio of the buzzer signal as shown in Table 4.12.7.3. Table 4.12.7.3 Duty ratio setting Level BDTY2 BDTY1 BDTY0 Level 1 (Max.) Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Level 8 (Min.) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Duty ratio by buzzer frequency (Hz) 4096.0 3276.8 2730.7 2340.6 2048.0 1638.4 1365.3 1170.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator) SHTPW: One-shot buzzer pulse width setting register (FF6DH•D0) Selects the output time of the one-shot buzzer. When "1" is written: 125 msec When "0" is written: 31.25 msec Reading: Valid Writing "1" into SHTPW causes the one-short output time to be set at 125 msec, and writing "0" causes it to be set to 31.25 msec. It does not affect normal buzzer output. At initial reset, this register is set to "0".
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit) 4.13 SVD (Supply Voltage Detection) Circuit 4.13.1 Configuration of SVD circuit The S1C6P466 has a built-in SVD (supply voltage detection) circuit, so that the software can find when the source voltage lowers. It is possible to check an external voltage drop as well as the supply voltage. Turning the SVD circuit ON/OFF and the SVD criteria voltage setting can be done with software. Figure 4.13.1.1 shows the configuration of the SVD circuit.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit) When the SVDON register is set to "1", source voltage or external voltage detection by the SVD circuit is executed. As soon as the SVDON register is reset to "0", the result is loaded to the SVDDT latch and the SVD circuit goes OFF. To obtain a stable detection result, the SVD circuit must be ON for at least l00 µsec. So, to obtain the SVD detection result, follow the programming sequence below. 1. 2. 3. 4.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit) 4.13.5 Programming notes (1) To obtain a stable detection result, the SVD circuit must be ON for at least l00 µsec. So, to obtain the SVD detection result, follow the programming sequence below. 1. 2. 3. 4. Set SVDON to "1" Maintain for 100 µsec minimum Set SVDON to "0" Read SVDDT (2) The SVD circuit should normally be turned OFF because SVD operation increase current consumption.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) 4.14 Interrupt and HALT The S1C6P466 provides the following interrupt functions.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) IPT0 NMI interrupt request Watchdog timer EIPT0 IPT1 EIPT1 ISIF Interrupt vector generation circuit EISIF K00 Program counter (low-order 4 bits) KCP00 SIK00 K01 KCP01 INT interrupt request SIK01 IK0 K02 EIK0 KCP02 Interrupt flag SIK02 K03 KCP03 SIK03 K10 KCP10 SIK10 K11 KCP11 Interrupt factor flag SIK11 IK1 K12 Interrupt mask register EIK1 KCP12 Input comparison register SIK12 Interrupt selection register K13 KCP13 SIK13
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) 4.14.1 Interrupt factor Table 4.14.1.1 shows the factors for generating interrupt requests. The interrupt flags are set to "1" depending on the corresponding interrupt factors. The CPU operation is interrupted when an interrupt factor flag is set to "1" if the following conditions are established. • The corresponding mask register is "1" (enabled) • The interrupt flag is "1" (EI) The interrupt factor flag is reset to "0" when "1" is written.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) 4.14.2 Interrupt mask The interrupt factor flags can be masked by the corresponding interrupt mask registers. The interrupt mask registers are read/write registers. They are enabled (interrupt authorized) when "1" is written to them, and masked (interrupt inhibited) when "0" is written to them. At initial reset, the interrupt mask register is set to "0". Table 4.14.2.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) 4.14.4 I/O memory of interrupt Tables 4.14.4.1(a) and (b) show the I/O addresses and the control bits for controlling interrupts. Table 4.14.4.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) Table 4.14.4.
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) 4.14.5 Programming notes (1) The interrupt factor flags are set when the interrupt condition is established, even if the interrupt mask registers are set to "0". (2) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag = "1") is set or the RETI instruction is executed unless the interrupt factor flag is reset.
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CHAPTER 5: PROM PROGRAMMING AND OPERATING MODE CHAPTER 5 PROM PROGRAMMING AND OPERATING MODE The S1C6P466 has built-in Flash EEPROMs as the code PROM and the data PROM that allow the developer to program the PROM data using the exclusive PROM writer (Universal ROM Writer II (S5U1C88000W1)). This chapter explains the PROM programmer that controls data writing and the writing mode. 5.1 Configuration of PROM Programmer The configuration of the PROM programmer is shown in Figure 5.1.1.
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CHAPTER 5: PROM PROGRAMMING AND OPERATING MODE VDD VDD SPRG, RXD, CLKIN 330 kΩ PORT XIN VSS 2 kΩ VDD TXD PORT VSS OUT VDD SCLK PULL_UP 330 kΩ PORT OUT VSS DATA_IN PORT_READ Fig. 5.1.
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CHAPTER 5: PROM PROGRAMMING AND OPERATING MODE 5.2 Operating Mode Three operating modes are available in the S1C6P466: one is for normal operation and the others are for programming. The operating mode is decided by the terminal setting at power-on or initial reset. When the SPRG terminal is set to Low, the S1C6P466 enters serial programming mode.
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CHAPTER 5: PROM PROGRAMMING AND OPERATING MODE The serial programming is performed using the 1 MHz clock supplied from the PROM writer to the CLKIN terminal. Take noise measure into consideration so that noise does not affect the clock line input to the CLKIN terminal when designing the target board. 5.2.3 Parallel programming mode The parallel programming can be performed by installing the S1C6P466 to the exclusive PROM writer via the adaptor socket.
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CHAPTER 6: DIFFERENCES FROM MASK ROM MODELS CHAPTER 6 DIFFERENCES FROM MASK ROM MODELS This chapter explains the differences in functions (except for the Flash EEPROM block) between the S1C6P466 and the mask ROM models (S1C63454, S1C63458 and S1C63466). 6.1 Mask Option The mask option items are fixed in the S1C6P466 as shown in the table below. Table 6.1.1 S1C6P466 mask option Mask option Setting OSC1 oscillation circuit Crystal oscillation (32.
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CHAPTER 6: DIFFERENCES FROM MASK ROM MODELS 6.2 Power Supply Since the S1C6P466 is produced using the Flash EEPROM process, the characteristics are different from those of the mask ROM models. Operating voltage range S1C6P466: S1C63454: S1C63458: S1C63466: 2.7 to 5.5 V 2.2 to 5.5 V (Min. 1.8 V when the OSC3 is not used) 2.2 to 5.5 V (Min. 1.8 V when the OSC3 is not used) 2.2 to 5.5 V (Min. 1.
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CHAPTER 6: DIFFERENCES FROM MASK ROM MODELS 6.3 PROM, RAM The S1C6P466 employs a Flash EEPROM for the internal PROM. The Flash EEPROM can be rewritten up to 100 times. Rewriting data is done at the user's own risk. Table 6.3.1 lists the internal memory size of each model. Table 6.3.
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CHAPTER 6: DIFFERENCES FROM MASK ROM MODELS 6.6 SVD Circuit The S1C6P466 has a built-in SVD (Supply Voltage Detection) circuit with the same configuration as that of the mask ROM model (S1C634xx). However, the mask option is fixed at "with external voltage detection". Table 6.6.1 lists the criteria voltages. Table 6.6.
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CHAPTER 7: SUMMARY OF NOTES CHAPTER 7 SUMMARY OF NOTES 7.1 Notes for Low Current Consumption The S1C6P466 contains control registers for each of the circuits so that current consumption can be reduced. These control registers reduce the current consumption through programs that operate the circuits at the minimum levels. The following lists the circuits that can control operation and their control registers. Refer to these when programming. Table 7.1.
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CHAPTER 7: SUMMARY OF NOTES 7.2 Summary of Notes by Function Here, the cautionary notes are summed up by function category. Keep these notes well in mind when programming. Memory and stack (1) Memory is not implemented in unused areas within the memory map. Further, some non-implementation areas and unused (access prohibition) areas exist in the display memory area and the peripheral I/O area. If the program that accesses these areas is generated, its operation cannot be guaranteed. Refer to Section 4.7.
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CHAPTER 7: SUMMARY OF NOTES Input port (1) When input ports are changed from low to high by pull-up resistors, the rise of the waveform is delayed on account of the time constant of the pull-up resistor and input gate capacitance. Hence, when fetching input ports, set an appropriate waiting time. Particular care needs to be taken of the key scan during key matrix configuration. Make this waiting time the amount of time or more calculated by the following expression.
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CHAPTER 7: SUMMARY OF NOTES Programmable timer (1) When reading counter data, be sure to read the low-order 4 bits (PTD00–PTD03, PTD10–PTD13) first. Furthermore, the high-order 4 bits (PTD04–PTD07, PTD14–PTD17) should be read within 0.73 msec (when fOSC1 is 32.768 kHz) of reading the low-order 4 bits (PTD00–PTD03, PTD10–PTD13). (2) The programmable timer actually enters RUN/STOP status in synchronization with the falling edge of the input clock after writing to the PTRUN0/PTRUN1 register.
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CHAPTER 7: SUMMARY OF NOTES SVD circuit (1) To obtain a stable detection result, the SVD circuit must be ON for at least l00 µsec. So, to obtain the SVD detection result, follow the programming sequence below. 1. 2. 3. 4. Set SVDON to "1" Maintain for 100 µsec minimum Set SVDON to "0" Read SVDDT (2) The SVD circuit should normally be turned OFF because SVD operation increase current consumption.
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CHAPTER 7: SUMMARY OF NOTES 7.3 Precautions on Mounting ● Oscillation characteristics change depending on conditions (board pattern, components used, etc.). In particular, when a ceramic oscillator or crystal oscillator is used, use the oscillator manufacturer's recommended values for constants such as capacitance and resistance. ● Disturbances of the oscillation clock due to noise may cause a malfunction.
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CHAPTER 7: SUMMARY OF NOTES ● In order to prevent generation of electromagnetic induction noise caused by mutual inductance, do not arrange a large current signal line near the circuits that are sensitive to noise such as the oscillation unit. ● When a signal line is parallel with a high-speed line in long distance or intersects a high-speed line, noise may generated by mutual interference between the signals and it may cause a malfunction.
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CHAPTER 8: BASIC EXTERNAL WIRING DIAGRAM CHAPTER 8 BASIC EXTERNAL WIRING DIAGRAM • Normal operation mode I/O Output Open Open K00–K03 K10–K13 P00–P03 P10 (SIN) P11 (SOUT) P12 (SCLK) P13 (SRDY) P20 P21 P22 (CL) P23 (FR) R00 R01 R02 (TOUT) R03 (FOUT) R10–R13 R20–R23 COM0 | COM16 Input SEG0 | SEG59 LCD panel 60 × 17 External voltage SVD CA CB CC CD CE CF C1 C2 C3 TEST VDD S1C6P466 [The potential of the substrate (back of the chip) is VSS.
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CHAPTER 8: BASIC EXTERNAL WIRING DIAGRAM • Serial programming mode (S1C88/S1C63 Serial Connector) I/O Output SEG0 | SEG59 Input COM0 | COM16 LCD panel 60 × 17 K00–K03 K10–K13 P00–P03 P10 (SIN) P11 (SOUT) P12 (SCLK) P13 (SRDY) P20 P21 P22 (CL) P23 (FR) R00 R01 R02 (TOUT) R03 (FOUT) R10–R13 R20–R23 External voltage SVD CA CB CC CD CE CF S1C6P466 [The potential of the substrate (back of the chip) is VSS.
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CHAPTER 9: ELECTRICAL CHARACTERISTICS CHAPTER 9 ELECTRICAL CHARACTERISTICS 9.1 Absolute Maximum Rating (VSS=0V) Item Rated value Unit Symbol Supply voltage -0.5 to 7.0 V VDD PROM power volrtage -0.5 to 7.0 VDDF V Input voltage (1) -0.5 to VDD + 0.3 VI V Input voltage (2) -0.5 to VDD + 0.
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CHAPTER 9: ELECTRICAL CHARACTERISTICS 9.3 DC Characteristics Unless otherwise specified: VDD=3.0V, VSS=0V, fOSC1=32.768kHz, Ta=25°C, VD1/VC1/VC2/VC4/VC5 are internal voltage, C1–C8=0.2µF Min. Typ. Condition Item Symbol 0.8·VDD K00–03, K10–13 High level input voltage (1) VIH1 P00–03, P10–13, P20–23 RESET, TEST 0.9·VDD High level input voltage (2) VIH2 VIL1 K00–03, K10–13 0 Low level input voltage (1) P00–03, P10–13, P20–23 VIL2 RESET, TEST 0 Low level input voltage (2) IIH K00–03, K10–13 VIH=3.
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CHAPTER 9: ELECTRICAL CHARACTERISTICS 9.4 Analog Circuit Characteristics and Power Current Consumption Unless otherwise specified: VDD=3.0V, VSS=0V, fOSC1=32.768kHz, CG=25pF, Ta=25°C, VD1/VC1/VC2/VC4/VC5 are internal voltage, C1–C8=0.2µF Condition Item Symbol Min. Typ. Max. Unit Connect 1 MΩ load resistor LC0–3="0" LCD drive voltage VC1 0.975 V (when VC1 standard is selected) LC0–3="1" between VSS and VC1 0.990 (without panel load) LC0–3="2" 1.005 LC0–3="3" 1.020 LC0–3="4" 1.035 LC0–3="5" 1.
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CHAPTER 9: ELECTRICAL CHARACTERISTICS Unless otherwise specified: VDD=3.0V, VSS=0V, fOSC1=32.768kHz, CG=25pF, Ta=25°C, VD1/VC1/VC2/VC4/VC5 are internal voltage, C1–C8=0.2µF Item Symbol Min. Typ. Max. Condition SVD voltage VSVD 0.95 1.05 1.20 SVDS0–3="0" (external)∗3 – SVDS0–3="1" – SVDS0–3="2" – SVDS0–3="3" – SVDS0–3="4" – SVDS0–3="5" – SVDS0–3="6" Typ. – Typ. SVDS0–3="7" ×0.93 – ×1.07 SVDS0–3="8" – SVDS0–3="9" 2.80 SVDS0–3="10" 2.90 SVDS0–3="11" 3.00 SVDS0–3="12" 3.10 SVDS0–3="13" 3.20 SVDS0–3="14" 3.
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CHAPTER 9: ELECTRICAL CHARACTERISTICS 9.5 Oscillation Characteristics The oscillation characteristics change depending on the conditions (components used, board pattern, etc.). Use the following characteristics as reference values. OSC1 crystal oscillation circuit Unless otherwise specified: VDD=3.0V, VSS=0V, fOSC1=32.
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CHAPTER 9: ELECTRICAL CHARACTERISTICS 9.6 Serial Interface AC Characteristics Clock synchronous master mode • During 32 kHz operation Condition: VDD=3.0V, VSS=0V, Ta=25°C, VIH1=0.8VDD, VIL1=0.2VDD, VOH=0.8VDD, VOL=0.2VDD Min. Typ. Item Symbol tsmd Transmitting data output delay time 10 tsms Receiving data input set-up time tsmh 5 Receiving data input hold time Max. 5 Unit µs µs µs Max. 200 Unit ns ns ns Max. 10 Unit µs µs µs Max. 500 Unit ns ns ns • During 1 MHz operation Condition: VDD=3.
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CHAPTER 9: ELECTRICAL CHARACTERISTICS 9.7 Timing Chart System clock switching ∗ 1 instruction execution time or longer ∗ VDC 2.5 msec min. ∗ OSCC 5 msec min. CLKCHG In the S1C6P466, the VDC register value does not affect the VD1 voltage level. However, note that the CPU clock cannot be switched from OSC1 to OSC3 using the CLKCHG register if the VDC register value is "0". Set the VDC register to "1" before switching the CPU clock from OSC1 to OSC3 in the S1C6P466.
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CHAPTER 9: ELECTRICAL CHARACTERISTICS 9.8 Characteristics Curves (reference value) High level output current (Rxx, Pxx, BZ, Typ. value) 0 0.1 0.2 VDD–VOH [V] 0.3 0.4 0.5 0.6 0.0 -1.0 -2.0 IOH [mA] -3.0 -4.0 VDD = 3V -5.0 -6.0 -7.0 VDD = 5V -8.0 -9.0 OSC1: 32.768kHz crystal oscillation, VSS = 0V, no panel load, CGX = 25pF, CGC = CDC = 30pF, C1–C8 = 0.
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CHAPTER 9: ELECTRICAL CHARACTERISTICS VC1/VC2 output voltage-temperature characteristic (Typ. value) 1.140 1.120 1.100 VC1 [V] -0.5 [mV/°C] 1.080 VC1 LC0–3 = 7 LPWR = 1 VCCHG = 0 1.060 1.040 1.020 1.000 -30 -10 10 30 Temperature [°C] 50 70 50 70 2.300 2.250 VC2 [V] 2.200 -1 [mV/°C] 2.150 VC2 LC0–3 = 7 LPWR = 1 VCCHG = 1 2.100 2.050 2.000 -30 -10 10 30 Temperature [°C] OSC1: 32.768kHz crystal oscillation, VDD = 3V, VSS = 0V, no panel load, CGX = 25pF, CGC = CDC = 30pF, C1–C8 = 0.
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CHAPTER 9: ELECTRICAL CHARACTERISTICS SVD external voltage detection level-supply voltage characteristic (Typ. value) 1.200 17 [mV/V] 1.000 VSVD [V] 0.800 0.600 SVDS0–3 = 0 (external voltage) 0.400 0.200 0.000 2.0 2.5 3.0 3.5 4.0 VDD [V] 4.5 5.0 5.5 6.0 OSC1: 32.768kHz crystal oscillation, Ta = 25°C, VSS = 0V, no panel load, CGX = 25pF, CGC = CDC = 30pF, C1–C8 = 0.2µF The external voltage detection level varies depending on the supply voltage.
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CHAPTER 9: ELECTRICAL CHARACTERISTICS Power current-supply voltage characteristic (HALT state) 16.0 VC1 standard LCD ON 14.0 VC2 standard 12.0 Ihalt [µA] 10.0 OSCC = 0 CLKCHG = 0 VDC = 0 8.0 6.0 LCD OFF 4.0 2.0 0.0 2.0 2.5 3.0 3.5 4.0 VDD [V] 4.5 5.0 5.5 6.0 OSC1: 32.
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CHAPTER 9: ELECTRICAL CHARACTERISTICS Power current-supply voltage characteristic (RUN state with OSC1 clock) 300 OSCC = 0 CLKCHG = 0 VDC = 0 250 LCD ON 200 Iexec [µA] LCD OFF 150 100 50 0 2.0 2.5 3.0 3.5 4.0 VDD [V] 4.5 5.0 5.5 6.0 OSC1: 32.768kHz crystal oscillation, Ta = 25°C, VSS = 0V, no panel load, CGX = 25pF, CGC = CDC = 30pF This graph is provided only for reference and the characteristic varies according to mounting conditions, parts used and the measurement environment.
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CHAPTER 10: PACKAGE CHAPTER 10 PACKAGE 10.1 Plastic Package QFP8-144pin (Unit: mm) 31.2±0.4 28±0.1 108 73 31.2±0.4 72 28±0.1 109 INDEX 3.35±0.1 37 1 36 0.65 0.3±0.1 0.15±0.05 0° 10° 0.6±0.2 0.1 3.65max 144 1.6 Notes: • The dimensions are subject to change without notice. • The QFP8-144pin package does not support parallel programming using an adapter socket. Only serial programming can be performed.
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CHAPTER 10: PACKAGE QFP17-144pin (Unit: mm) 22±0.4 20±0.1 108 73 22±0.4 72 20±0.1 109 INDEX 144 37 0.5 +0.1 36 0.2–0.05 3max 2.7±0.1 1 0.1 0.15±0.05 0° 10° 0.5±0.2 1 Note: The dimensions are subject to change without notice.
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CHAPTER 10: PACKAGE 10.2 Ceramic Package for Test Samples QFP8-144pin (Unit: mm) 36.93±0.30 28.00±0.28 73 72 144 37 28.00±0.28 109 1 36 0.30±0.05 0.20 Typ. 0.15 0.65±0.05 3.05 Max. 36.93±0.30 108 1.20 Typ. Note: The QFP8-144pin package does not support parallel programming using an adapter socket. Only serial programming can be performed.
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CHAPTER 10: PACKAGE QFP17-144pin (Unit: mm) 22.00±0.25 19.20±0.19 73 72 144 37 19.20±0.19 109 1 22.00±0.25 108 36 0.20 0.15 2.80 Max 0.50 0.50±0.
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CHAPTER 11: PAD LAYOUT CHAPTER 11 PAD LAYOUT 35 30 25 20 15 10 5 1 Die No. 11.1 Diagram of Pad Layout 140 40 135 45 130 50 125 55 (0, 0) X 5.30 mm Y 120 60 115 65 110 70 75 80 85 90 95 100 105 5.
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CHAPTER 11: PAD LAYOUT 11.2 Pad Coordinates No.
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APPENDIX A PROM PROGRAMMING APPENDIX A PROM PROGRAMMING A.1 Outline of Writing Tools The following tools are provided for writing user data to the Flash EEPROM built into the S1C6P466. Select one according to the development environment.
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APPENDIX A PROM PROGRAMMING A.2 Serial Programming (S1C88/S1C63 Serial Connector) A.2.1 Serial programming environment (S1C88/S1C63 Serial Connector) Prepare a personal computer system as a host computer, the exclusive PROM writing tools and the data for writing into the built-in Flash microcomputer.
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APPENDIX A PROM PROGRAMMING A.2.2 System connection and setup for serial programming (S1C88/S1C63 Serial Connector) Connect the Universal Writer to the personal computer and install the S1C88/S1C63 Serial Connector to the Universal Writer.
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APPENDIX A PROM PROGRAMMING A.2.3 Serial programming procedure (S1C88/S1C63 Serial Connector) (1) Connecting the system Connect the system as shown in Section A.2.2, "System connection and setup for serial programming (S1C88/S1C63 Serial Connector)". (2) Power on Turn the personal computer on then the Universal Writer (POWER SW is located on the side panel). (3) Checking the serial port configuration Check to see that the serial port is assigned to COM1 in the personal computer.
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APPENDIX A PROM PROGRAMMING (7) Connecting the target board Connect the target board to the S1C88/S1C63 Serial Connector. Refer to Section A.2.4, "Connection diagram for serial programming (S1C88/S1C63 Serial Connector)", for connection. Note: Do not turn on the power of the target board since the PROM programming power (5 V) is supplied from the Universal Writer. (8) Erasing PROM Clear (erase) the contents of the PROM (code PROM and data PROM) and perform erase check using the following command.
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APPENDIX A PROM PROGRAMMING A.2.4 Connection diagram for serial programming (S1C88/S1C63 Serial Connector) Connecting to target board Figure A.2.4.1 shows the connection on the target board and Table A.2.4.1 lists the signal specifications. Universal Writer interface connector VDD VDDF CLK VSS SCLK VSS RXD VSS TXD VSS RESET VSS SPRG VSS Reserved Reserved Microcomputer on target board 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VDD CLKIN SCLK RXD TXD RESET SPRG VSS Fig. A.2.4.
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APPENDIX A PROM PROGRAMMING Sample connection diagram for serial programming (S1C88/S1C63 Serial Connector) I/O Output K00–K03 K10–K13 P00–P03 P10 (SIN) P11 (SOUT) P12 (SCLK) P13 (SRDY) P20 P21 P22 (CL) P23 (FR) R00 R01 R02 (TOUT) R03 (FOUT) R10–R13 R20–R23 COM0 | COM16 Input SEG0 | SEG59 LCD panel 60 × 17 External voltage SVD CA CB CC CD CE CF S1C6P466 [The potential of the substrate (back of the chip) is VSS.
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APPENDIX A PROM PROGRAMMING A.3 Parallel Programming A.3.1 Parallel programming environment Prepare a personal computer system as a host computer and the data for writing into the built-in Flash microcomputer.
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APPENDIX A PROM PROGRAMMING A.3.2 System connection and setup for parallel programming Connect the Universal Writer to the personal computer and install the S1C6P466 Adapter Socket to the Universal Writer. S1C6P466 Adapter Socket READY 466 CKET E0C63P ADAPTER SO POWER I O FU SE OLNROM WRITER II PIVESRSA EUN PO W ER P2 VSS TXD RXD CLK1M SCLK VPP AC IN RS-232C RS232C DSW RS-232C cable ∗ The name 'Universal ROM Writer II' on the development tool is the old name of the product. Power cable Fig.
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APPENDIX A PROM PROGRAMMING A.3.3 Parallel programming procedure (1) Connecting the system Connect the system as shown in Section A.3.2, "System connection and setup for parallel programming". (2) Power on Turn the personal computer on then the Universal Writer (POWER SW is located at the side panel). (3) Checking the serial port configuration Check to see that the serial port is assigned to COM1 in the personal computer.
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APPENDIX A PROM PROGRAMMING (7) Mounting the S1C6P466 Mount the IC as the figure below. S1C6P466 1 pin READY E0C63P466 ADAPTER SOCKET ∗ The name 'E0C63P466 Adapter Socket' on the development tool is the old name of the product. Note: Be aware that the IC may be damaged if parallel programming is performed by installing the IC to the S1C6P466 Adapter Socket in the wrong direction.
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APPENDIX A PROM PROGRAMMING (11) Terminating the Control Software Execute the QUIT command to terminate the control software. 63P466:Q Note: Restarting the control software after it has been terminated without the QUIT command, for instance the MS-DOS prompt window is closed, may cause an error such as "RAM CLEAR ERROR". In this case, turn the Universal Writer off once and then turn on before starting up the control software.
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APPENDIX A PROM PROGRAMMING A.4 Universal ROM Writer II (S5U1C88000W1) Specifications A.4.1 Outline of Universal ROM Writer II specifications This is a PROM writer for built-in Flash microcomputers. In the onboard serial programming mode, the SIO Cable supplied with the Universal Writer or the S1C88/S1C63 Serial Connector is used to connect the Universal Writer and the user target board that has a built-in Flash microcomputer installed.
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APPENDIX A PROM PROGRAMMING A.4.2 Detailed description of the Universal ROM Writer II commands This section explains the commands which can be used in RW63P466. The following symbols have been used in the explanation: _ indicates space A parameter enclosed by [ ] can be omitted , indicates selection item indicates Enter key 1 WRITE command (code PROM) for parallel programming Operation: WI [ _ / V ] Option: /V .................. Verifies data from the code PROM start address after writing.
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APPENDIX A PROM PROGRAMMING 5 VERIFY command (code PROM) for parallel programming Operation: VI Description: Verifies the contents of the code PROM in the S1C6P466 on the socket and the contents of the buffer RAM in the PROM writer. The accessed code PROM address is displayed during verification. When an error occurs, verification stops. At this time, the address and data of the code PROM and the buffer RAM data are displayed. To resume verification, press Enter .
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APPENDIX A PROM PROGRAMMING 12 PROTECT command for parallel programming Operation: PROTECT Description: Sets the protect bit of the PROM in the S1C6P466 on the socket. When the protect bit has been set, execution of all the commands except for ERSA are disabled. 13 WRITE command (code PROM) for serial programming Operation: FWI [ _ / V ] Option: /V .................. Verifies data from the code PROM start address after writing.
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APPENDIX A PROM PROGRAMMING 17 VERIFY command (code PROM) for serial programming Operation: FVI Description: Verifies the contents of the S1C6P466 code PROM on the target board connected to the PROM writer and the contents of the buffer RAM in the PROM writer. The accessed code PROM address is displayed during verification. When an error occurs, verification stops. At this time, the address and data of the code PROM and the buffer RAM data are displayed. To resume verification, press Enter .
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APPENDIX A PROM PROGRAMMING 23 ERASE CHECK command (data PROM) for serial programming Operation: FEC Description: Checks that the S1C6P466 data PROM on the target board connected to the PROM writer has been erased. The data PROM address is displayed during checking. When an error occurs, erase check stops. At this time, the address and data of the data PROM are displayed. To resume erase check, press Enter .
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APPENDIX A PROM PROGRAMMING 28 SAVE command (for data PROM file) Operation: SC _ file name Option: file name ...... File name to be saved (without extension) Description: Saves the data PROM contents in the buffer RAM of the PROM writer into a file with the specified name and .CSA extension. The file name should be specified without the extension. Example: SS_c3466001 ..... Saves the data PROM contents into the C3466001.CSA file.
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APPENDIX A PROM PROGRAMMING 30 DUMP command (for data PROM) Operation: DC [ _ address 1 [ _ address 2 ] ] [_/C] Option: address 1 ...... Dump start address Can be specified within the range of 0000H to 07E0H in 20H units. address 2 ...... Dump end address Can be specified within the range of 001FH to 07FFH in 20H units. /C .................. Displays in HEX file (C3xxxyyy.CSA) format Description: Displays the data PROM contents in the buffer RAM with the specified format.
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APPENDIX A PROM PROGRAMMING 33 COMMAND HISTORY Operation: ↑ ↓ Description: Previously input commands are displayed. A command displayed can be re-executed by selecting with ↑ or ↓ and pressing Enter . Up to 20 commands can be stored in the buffer. 34 TEMPLATE (MS-DOS) Operation: f1 f3 Description: Previously input command can be re-displayed. Pressing f1 displays the characters of the command one by one, and pressing f3 displays all the characters at once.
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APPENDIX A PROM PROGRAMMING A.4.3 List of Universal ROM Writer II commands No.
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APPENDIX A PROM PROGRAMMING A.4.4 Universal ROM Writer II error messages Error message PROM WRITER NOT POWER ON Description The PROM writer does not respond when a start-up check command is issued. SUM CHECK ERROR An IPL checksum error has occurred in the PROM writer. RAM R/W ERROR An error has occurred during R/W check for the RAM. FILE DATA FORMAT ERROR There is an error in the data format of the file to be transferred. FILE DATA SUMCHECK ERROR There is an error in the checksum data of the file.
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APPENDIX A PROM PROGRAMMING A.5 Flash EEPROM Programming Notes (1) The programing voltage of the S1C6P466 PROM must be 5 V. (2) Since PROM programming uses a 5-V power source, be careful of the voltage ratings of the parts on the target board. (3) Make sure that the READY LED on the S1C88/S1C63 Serial Connector or S1C6P466 Adapter Socket is lit when connecting (mounting) or disconnecting (removing) the target board (S1C6P466).
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APPENDIX B S5U1C63000P MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63404/454/455/458/466/P466) APPENDIX B S5U1C63000P MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63404/454/455/458/466/P466) This manual describes how to use the Peripheral Circuit Board for the S1C63404/454/455/458/466/P466 (S5U1C63000P), which provides emulation functions when mounted on the debugging tool for the S1C63 Family of 4-bit single-chip microcomputers, the ICE (S5U1C63000H1/S5U1C63000H2).
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APPENDIX B S5U1C63000P MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63404/454/455/458/466/P466) (4) Register monitor pins These pins correspond one-to-one to the registers listed below. The pin outputs a high for logic "1" and a low for logic "0". Monitor LED Pin No. Name LED No.
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APPENDIX B S5U1C63000P MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63404/454/455/458/466/P466) (7) RESET switch This switch initializes the internal circuits of this board and feeds a reset signal to the ICE. (8) Monitor pins and external part connecting socket These parts are currently unused. (9) IOSEL2 When downloading circuit data, set IOSEL2 to the "E" position. Otherwise, set to the "D" position.
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APPENDIX B S5U1C63000P MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63404/454/455/458/466/P466) B.2 Connecting to the Target System This section explains how to connect the S5U1C63000P to the target system. To connect this board (S5U1C63000P) to the target system, use the I/O connecting cables supplied with the board (80-pin/40-pin × 2, flat type). Take care when handling the connectors, since they conduct electrical power (VDD = +3.3 V).
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APPENDIX B S5U1C63000P MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63404/454/455/458/466/P466) Table B.2.1 I/O connector pin assignment 40-pin CN1-1 connector 40-pin CN1-2 connector No. Pin name No. Pin name 1 VDD (=3.3 V) 1 VDD (=3.3 V) 2 VDD (=3.3 V) 2 VDD (=3.
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APPENDIX B S5U1C63000P MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63404/454/455/458/466/P466) B.3 Usage Precautions To ensure correct use of this board (S5U1C63000P), please observe the following precautions. B.3.1 Operational precautions (1) Before inserting or removing cables, turn off power to all pieces of connected equipment. (2) Do not turn on power or load mask option data if all of the input ports (K00–K03) are held low. Doing so may activate the multiple key entry reset function.
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APPENDIX B S5U1C63000P MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63404/454/455/458/466/P466) (3) Functional precautions - There is a finite delay time from the point at which the LCD power supply circuit (LPWR) turns on until an LCD drive waveform is output. On this board, this delay is set to approx. 125 msec, which differs from that of the actual IC. Refer to the technical manual for the S1C63404/454/455/458/466/ P466.
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APPENDIX B S5U1C63000P MANUAL (PERIPHERAL CIRCUIT BOARD FOR S1C63404/454/455/458/466/P466) ∗1 When this tool is used for the S1C63404/458/466/P466: - Although the S1C63404/458/466/P466 has a function for detecting externally sourced voltages, this board is unable to detect externally sourced voltages. The SVD function is realized by artificially varying the power supply voltage using the VSVD control on this board.
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