Specifications

Table Of Contents

5 OPERATIONS AND FUNCTIONS OF THE S5U1C63000H6

EPSON

S5U1C63000H6 MANUAL

(S1C63 Family In-Circuit Emulator)

(3) TRNIN input terminal

By connecting a signal line of the target system to this terminal, the signal status is stores in the trace memory

as a trace information. “1” is written to the trace memory when no signal is connected or the signal goes high,

or “0” is written when the signal goes low. The signal level is sampled at the rising edge of T4 state.

(4) BRKIN input terminal

A break occurs when a low level signal is input to this terminal while the target program is running. To use this

terminal for the break function, the low level pulse must be 20 ms or longer. By connecting the TRGOUT out-

put terminal to the BRKIN input terminal, breaks can be occurred according to the trace trigger conditions.

Note: The above output terminals outputs 5.0 V. The input terminals have a pull-up resistor and allow

input of a signal within 3.3 V to 5.0 V.

5.4 Display During Execution and During Break

The S5U1C63000H6 control processor monitors the execution status of the S1C63000 CPU while the target pro-

gram is running. It displays the S1C63000 CPU’s execution status in every 500 ms when the on-the-fly display

mode is specified. The program counter value that is displayed during break shows the address to be executed in the

next step. The register contents displayed are the values when the previous break occurred.

5.5 Break Commands

The S5U1C63000H6 has abundant break functions.

(1) Program counter break

This break function is specified by the BP command. When the program counter of the S1C63000 CPU coin-

cides with the specified address, a break occurs before executing the instruction. Multiple program counter val-

ues (up to maximum size of program memory) can be specified as break points.

(2) Program counter sequential break

This break function is specified by the BS command. A break occurs when the program counter of the

S1C63000 CPU counts three addresses in the specified order. The pass counter can be specified for the last

address. The sequence (address 1 coincidence) → (address 2 coincidence) → (address 3 counted by specified

times) breaks the execution.

(3) Break by data access

This break function is specified by the BD command. A break occurs immediately after the target program ac-

cesses the data memory in the specified condition (address, data and read or write operation). It is possible to

specify a range for the address condition, a mask in bit units for the data condition and a mask for the read/

write condition. This specification can set one break point only.

(4) Break by register value

This break function is specified by the BR command. When the register values of the S1C63000 CPU coincide

with the specified values, a break occurs immediately after the instruction is executed. A/B register, E/I/C/Z

flag and X/Y register values can be specified as a break condition. It is also possible to specify masking on each

The above break functions (1, 2, 3 and 4) can be independently specified. When the target program is executed with

all the BP, BS, BD and BR commands specified, a break occurs by meeting any condition.