User`s manual

8: REGISTERS
1-82 EPSON S1D13504 SERIES HARDWARE FUNCTIONAL
SPECIFICATION (X19A-A-002-17)
bits 3–2 RAS# Precharge Timing (NRP) Bits [1:0]
Minimum Memory Timing for RAS precharge
These bits select the DRAM RAS# Precharge timing parameter, tRP. These bits specify
the number (NRP) of MCLK periods (TM) used to create tRP - see the following formulae.
Note, these formulae assume an MCLK duty cycle of 50 ± 5%.
NRP = 1 if (tRP/TM) < 1
= 1.5 if 1 ≤ (tRP/TM) < 1.45
= 2 if (tRP/TM) ≥ 1.45
The resulting tRP is related to NRP as follows:
tRP = (NRP + 0.5) TM if FPM refresh cycle and NRP = 1 or 2
tRP = (NRP) TM for all other
Optimal DRAM Timing
The following table contains the optimally programmed values of NRC, NRP, and NRCD
for different DRAM types, at maximum MCLK frequencies.
bit 0 Reserved
Must be set to 0.
bit 7 Display FIFO Disable
When this bit = 1 the display FIFO is disabled and all data outputs are forced to zero (i.e.
the screen is blanked). This allows the S1D13504 to be dedicated to service CPU to mem-
ory accesses. When this bit = 0 the display FIFO is enabled.
bits 4–0 Display FIFO Threshold Bits [4:0]
These bits should be set to a value of 10h upon initialization as this provides the best
overall performance for all display modes.
Table 8-12 RAS#-to-CAS# Delay Timing Select
REG[22h] Bit 4 NRCD RAS# - CAS# Delay (tRCD)
0 2 2 TM
1 1 1 TM
Table 8-13 RAS# Precharge Timing Select
REG[22h] Bits [3:2] NRP RAS# Precharge Width (tRP)
00 2 2 T
M
01 1.5 1.5 TM
10 1 1 TM
11 Reserved Reserved
Table 8-14 Optimal NRC, NRP, and NRCD Values at Maximum MCLK Frequency
DRAM Type
DRAM Speed
(ns)
TM
(ns)
NRC
(#MCLK)
NRP
(#MCLK)
NRCD
(#MCLK)
EDO
50 25 4 1.5 2
60 30 4 1.5 2
70 33 5 2 2
FPM
60 40 4 1.5 2
70 50 3 1.5 1
Performance Enhancement Register 1
REG[23h] RW
Display FIFO
Disable
n/a n/a
Display FIFO
Threshold
Bit 4
Display FIFO
Threshold
Bit 3
Display FIFO
Threshold
Bit 2
Display FIFO
Threshold
Bit 1
Display FIFO
Threshold
Bit 0