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8: REGISTERS

S1D13504 SERIES HARDWARE FUNCTIONAL EPSON 1-79

SPECIFICATION (X19A-A-002-17)

bit 7 GPIO7 Pin IO Status

When GPIO7 is conﬁgured as an output, a “1” in this bit drives GPIO7 to high and a “0”

in this bit drives GPIO7 to low. When GPIO7 is conﬁgured as an input, a read from this

bit returns the status of GPIO7. Note the MD8 pin must be high at the rising edge of

RESET# to enable GPIO7, otherwise the DACWR# pin is controlled automatically and

this bit will have no effect on hardware.

bit 6 GPIO6 Pin IO Status

When GPIO6 is conﬁgured as an output, a “1” in this bit drives GPIO6 to high and a “0”

in this bit drives GPIO6 to low. When GPIO6 is conﬁgured as an input, a read from this

bit returns the status of GPIO6. Note the MD8 pin must be high at the rising edge of

RESET# to enable GPIO6, otherwise the DACP0 pin is controlled automatically and this

bit will have no effect on hardware.

bit 5 GPIO5 Pin IO Status

When GPIO5 is conﬁgured as an output, a “1” in this bit drives GPIO5 to high and a “0”

in this bit drives GPIO5 to low. When GPIO5 is conﬁgured as an input, a read from this

bit returns the status of GPIO5. Note the MD8 pin must be high at the rising edge of

RESET# to enable GPIO5, otherwise the BLANK# pin is controlled automatically and

this bit will have no effect on hardware.

bit 4 GPIO4 Pin IO Status

When GPIO4 is conﬁgured as an output, a “1” in this bit drives GPIO4 to high and a “0”

in this bit drives GPIO4 to low. When GPIO4 is conﬁgured as an input, a read from this

bit returns the status of GPIO4. Note the MD8 pin must be high at the rising edge of

RESET# to enable GPIO4, otherwise the DACRD# pin is controlled automatically and

this bit will have no effect on hardware.

bit 3 GPIO3 Pin IO Status

When GPIO3 is conﬁgured as an output, a “1” in this bit drives GPIO3 to high and a “0”

in this bit drives GPIO3 to low. When GPIO3 is conﬁgured as an input, a read from this

bit returns the status of GPIO3. Note the MD[7:6] pins must be properly conﬁgured at the

rising edge of RESET# to enable GPIO3, otherwise the MA9 pin is controlled automati-

cally and this bit will have no effect on hardware.

bit 2 GPIO2 Pin IO Status

When GPIO2 is conﬁgured as an output, a “1” in this bit drives GPIO2 to high and a “0”

in this bit drives GPIO2 to low. When GPIO2 is conﬁgured as an input, a read from this

bit returns the status of GPIO2. Note the MD[7:6] pins must be properly conﬁgured at the

rising edge of RESET# to enable GPIO2, otherwise the MA11 pin is controlled automati-

cally and this bit will have no effect on hardware.

bit 1 GPIO1 Pin IO Status

When GPIO1 is conﬁgured as an output, a “1” in this bit drives GPIO1 to high and a “0”

in this bit drives GPIO1 to low. When GPIO1 is conﬁgured as an input, a read from this

bit returns the status of GPIO1. Note the MD[7:6] pins must be properly conﬁgured at the

rising edge of RESET# to enable GPIO1, otherwise the MA10 pin is controlled automati-

cally and this bit will have no effect on hardware.

bit 0 GPIO0 Pin IO Status

When GPIO0 is conﬁgured as an output, a “1” in this bit drives GPIO0 to high and a “0”

in this bit drives GPIO0 to low. When GPIO0 is conﬁgured as an input, a read from this

bit returns the status of GPIO0.

GPIO Status / Control Register 0

REG[20h] RW

GPIO7 Pin

IO Status

GPIO6 Pin

IO Status

GPIO5 Pin

IO Status

GPIO4 Pin

IO Status

GPIO3 Pin

IO Status

GPIO2 Pin

IO Status

GPIO1 Pin

IO Status

GPIO0 Pin

IO Status