User`s manual

8: REGISTERS
S1D13504 SERIES HARDWARE FUNCTIONAL EPSON 1-73
SPECIFICATION (X19A-A-002-17)
This register is used to control the horizontal pixel panning of screen 1 and screen 2. Each
screen can be independently panned to the left by programming its respective Pixel Pan-
ning Bits to a non-zero value. This value represents the number of pixels panned. The
maximum pan value is dependent on the display mode as shown in the table below.
Smooth horizontal panning can be achieved by a combination of this register and the Dis-
play Start Address register. See Section 10, “Display Configuration” on page 88 and
“S1D13504 Programming Notes and Examples”, document number S19A-G-002-xx,
Section 4 for details.
bits 7–4 Screen 2 Pixel Panning Bits [3:0]
Pixel panning bits for screen 2.
bits 3–0 Screen 1 Pixel Panning Bits [3:0]
Pixel panning bits for screen 1.
Pixel Panning Register
REG[18h] RW
Screen 2 Pixel
Panning Bit 3
Screen 2 Pixel
Panning Bit 2
Screen 2 Pixel
Panning Bit 1
Screen 2 Pixel
Panning Bit 0
Screen 1 Pixel
Panning Bit 3
Screen 1 Pixel
Panning Bit 2
Screen 1 Pixel
Panning Bit 1
Screen 1 Pixel
Panning Bit 0
Table 8-8 Pixel Panning Selection
Number of Bits-Per-Pixe Screen 2 Pixel Panning Bits Used
1 Bits [3:0]
2 Bits [2:0]
4 Bits [1:0]
8 Bit 0
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