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8: REGISTERS

1-72 EPSON S1D13504 SERIES HARDWARE FUNCTIONAL

SPECIFICATION (X19A-A-002-17)

REG[13h] bits 7–0, REG[14h] bits 7–0, REG[15h] bits 3–0

Screen 2 Start Address Bits [19:0]

This register forms the 20-bit address for the starting word of the screen 2 image in the

display buffer. Note that this is a word address. An entry of 0000h into these registers rep-

resents the ﬁrst word of display memory, an entry of 0001h represents the second word of

display memory, and so on. See Section 10, “Display Conﬁguration” on page 88 for

details.

REG[16] bits 7-0, REG[17] bits 1-0

Memory Address Offset Bits [9:0]

These bits are the 10-bit address offset from the starting word of line “n” to the starting

word of line “n + 1”. This value is applied to both screen 1 and screen 2.

Note: This value is in words and must be programmed ≥ REG[04h].

A virtual image can be formed by setting this register to a value greater than the width of

the display. The displayed image is a window into the larger virtual image.

See Section 10, “Display Conﬁguration” on page 88 for details.

Screen 2 Display Start Address Register 0

REG[13h] RW

Start Address

Bit 7

Start Address

Bit 6

Start Address

Bit 5

Start Address

Bit 4

Start Address

Bit 3

Start Address

Bit 2

Start Address

Bit 1

Start Address

Bit 0

Screen 2 Display Start Address Register 1

REG[14h] RW

Start Address

Bit 15

Start Address

Bit 14

Start Address

Bit 13

Start Address

Bit 12

Start Address

Bit 11

Start Address

Bit 10

Start Address

Bit 9

Start Address

Bit 8

Screen 2 Display Start Address Register 2

REG[15h] RW

n/a n/a n/a n/a

Start Address

Bit 19

Start Address

Bit 18

Start Address

Bit 17

Start Address

Bit 16

Memory Address Offset Register 0

REG[16h] RW

Memory

Address

Offset Bit 7

Memory

Address

Offset Bit 6

Memory

Address

Offset Bit 5

Memory

Address

Offset Bit 4

Memory

Address

Offset Bit 3

Memory

Address

Offset Bit 2

Memory

Address

Offset Bit 1

Memory

Address

Offset Bit 0

Memory Address Offset Register 1

REG[17h] RW

n/a n/a n/a n/a n/a n/a

Memory

Address

Offset Bit 9

Memory

Address

Offset Bit 8