User`s manual

8: REGISTERS
S1D13504 SERIES HARDWARE FUNCTIONAL EPSON 1-65
SPECIFICATION (X19A-A-002-17)
8.2 Register Descriptions
Note: Unless specified otherwise, all register bits are reset to 0 during power up. Reserved bits should be
written 0 when programming unless otherwise noted.
8.2.1 Revision Code Register
bits 7–2 Product Code Bits [5:0]
This is a read-only register that indicates the product code of the chip. The product code is
000001.
bits 1–0 Revision Code Bits [1:0]
This is a read-only register that indicates the revision code of the chip. The revision code
is 00.
8.2.2 Memory Configuration Registers
bits 6–4 DRAM Refresh Rate Select Bits [2:0]
These bits specify the amount of divide from the input clock (CLKI) to generate the
DRAM refresh clock rate, which is equal to 2
(ValueOfTheseBits + 6)
.
bit 2 WE# Control
When this bit = 1, 2-WE# DRAM is selected. When this bit = 0 2-CAS# DRAM is
selected.
bit 0 Memory Type
When this bit = 1, FPM-DRAM is selected. When this bit = 0, EDO-DRAM is selected.
This bit should be changed only when there are no read/write DRAM cycles. This condi-
tion occurs when both the Display FIFO is disabled (REG[23h] bit 7 = 1) and the Half
Frame Buffer is disabled (REG[1Bh] bit 0 = 1). For programming information, see
“S1D13504 Programming Notes and Examples”, document number S19A-G-002-xx.
Revision Code Register
REG[00h] RO
Product Code
Bit 5
Product Code
Bit 4
Product Code
Bit 3
Product Code
Bit 2
Product Code
Bit 1
Product Code
Bit 0
Revision Code
Bit 1
Revision Code
Bit 0
Memory Configuration Register
REG[01h] RW
n/a
Refresh Rate
Bit 2
Refresh Rate
Bit 1
Refresh Rate
Bit 0
n/a WE# Control n/a Memory Type
Table 8-2 DRAM Refresh Rate Selection
Refresh Rate Bits [2:0] CLKI Divide Amount
Refresh Rate for 33MHz
CLKI
DRAM Refresh
Time/256 Cycles
000 64 520 kHz 0.5 ms
001 128 260 kHz 1 ms
010 256 130 kHz 2 ms
011 512 65 kHz 4 ms
100 1024 33 kHz 8 ms
101 2048 16 kHz 16 ms
110 4096 8 kHz 32 ms
111 8192 4 kHz 64 ms