User`s manual

7: A.C. CHARACTERISTICS
1-60 EPSON S1D13504 SERIES HARDWARE FUNCTIONAL
SPECIFICATION (X19A-A-002-17)
Figure 7-43 TFT A.C. Timing
Note: 1. Ts = pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4
(see REG[19h] bits [1:0])
2. t
6min = [((REG[04h] bits [6:0]) + 1)∗8 + ((REG[05h] bits [4:0]) + 1)∗8] Ts
3. t
7min = [((REG[07h] bits [3:0]) + 1)∗8] Ts
4. t
8 min = [((REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1) + ((REG[0Ah] bits [5:0]) + 1)] lines
5. t
9min = [((REG[0Ch] bits [2:0]) + 1)] lines
6. t
10min = [((REG[04h] bits [6:0]) + 1)∗8] Ts
7. t
12min = [((REG[06h] bits [4:0]) + 1)∗8] Ts
8. t
14min = [((REG[04h] bits [6:0]) + 1)∗8] Ts
9. t
15min = [((REG[06h] bits [4:0]) + 1)∗8 - 2] Ts
10. t
17min = [((REG[05h] bits [4:0]) + 1)∗8 - ((REG[06h] bits [4:0]) + 1)∗8 + 2]
Table 7-33 TFT A.C. Timing
Symbol Parameter Min. Typ. Max. Units
t1
FPSHIFT period
1 Ts (note 1)
t2
FPSHIFT pulse width high
0.45 Ts
t3
FPSHIFT pulse width low
0.45 Ts
t4
data setup to FPSHIFT falling edge
0.45 Ts
t5
data hold from FPSHIFT falling edge
0.45 Ts
t6
FPLINE cycle time
note 2
t7
FPLINE pulse width low
note 3
t8
FPFRAME cycle time
note 4
t9
FPFRAME pulse width low
note 5
t10
horizontal display period
note 6
t11
FPLINE setup to FPSHIFT falling edge
0.45 Ts
t12
FPFRAME falling edge to FPLINE falling edge phase difference
note 7
t13
DRDY to FPSHIFT falling edge setup time
0.45 Ts
t14
DRDY pulse width
note 8
t15
DRDY falling edge to FPLINE falling edge
note 9
t16
DRDY hold from FPSHIFT falling edge
0.45 Ts
t17
FPLINE falling edge to DRDY active
note 10 250 Ts
t12
t7
FPLINE
t8
t6
FPFRAME
DRDY
FPSHIFT
640
t9
FPLINE
21 639
R[5:1]
t13
t2 t3
t16
t4 t5
t14
t15
t1
t11
t10
G[5:0]
B[5:1]
Note: DRDY is used to indicate the first pixel.
t17