User`s manual

7: A.C. CHARACTERISTICS
S1D13504 SERIES HARDWARE FUNCTIONAL EPSON 1-59
SPECIFICATION (X19A-A-002-17)
7.4.12 16-Bit TFT Panel Timing
Figure 7-42 16-Bit TFT Panel Timing
VDP = Vertical Display Period = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1
VNDP = Vertical Non-Display Period = (REG[0Ah] bits [5:0]) +1
HDP = Horizontal Display Period = ((REG[04h] bits [6:0]) + 1)∗8Ts
HNDP = Horizontal Non-Display Period = HNDP
1 + HNDP2 = ((REG[05h] bits [4:0]) + 1)∗8Ts
FPFRAME
FPLINE
LINE1 LINE480
1-1
1-1
1-1
1-2
1-2
1-2
1-640
1-640
1-640
FPLINE
FPSHIFT
DRDY
R[5:1], G[5:0], B[5:1]
R[5:1]
G[5:0]
B[5:1]
VDP
DRDY
Note: Example Timing for 640x480 panel. DRDY is used to indicate the first pixel.
VNDP
HDP
HNDP1
HNDP2
LINE480