User`s manual

7: A.C. CHARACTERISTICS
1-48 EPSON S1D13504 SERIES HARDWARE FUNCTIONAL
SPECIFICATION (X19A-A-002-17)
Figure 7-31 Single Color 8-Bit Panel A.C. Timing (Format 1)
Note: 1. Ts = pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4
(see REG[19h] bits [1:0])
2. t
1min = t4min - 9Ts
3. t
4min = [((REG[04h] bits [6:0]) + 1)∗8 + ((REG[05h] bits [4:0]) + 1)∗8] Ts
4. t
5min = [((REG[05h] bits [4:0]) + 1)∗8 - 27]+T11 Ts
5. t
5min = [((REG[05h] bits [4:0]) + 1)∗8 - 27] Ts
6. t
8min = [((REG[05h] bits [4:0]) + 1)∗8 - 18] Ts
7. t
8min = [((REG[05h] bits [4:0]) + 1)∗8 - 18]+T11 Ts
Table 7-27 Single Color 8-Bit Panel A.C. Timing (Format 1)
Symbol Parameter Min. Typ. Max. Units
t1
FPFRAME setup to FPLINE falling edge
note 2
t2
FPFRAME hold from FPLINE falling edge
9 Ts (note 1)
t3
FPLINE pulse width
9Ts
t4
FPLINE period
note 3
t5a
FPSHIFT2 falling edge to FPLINE rising edge
note 4
t5b
FPSHIFT falling edge to FPLINE rising edge
note 5
t6
FPLINE falling edge to FPSHIFT2 rising, FPSHIFT falling edge
t14 + 2
Ts
t7
FPSHIFT2, FPSHIFT period
4Ts
t8a
FPSHIFT falling edge to FPLINE falling edge
note 6
t8b
FPSHIFT2 falling edge to FPLINE falling edge
note 7
t9
FPLINE falling edge to FPSHIFT rising edge
18 Ts
t10
FPSHIFT2, FPSHIFT pulse width high
2Ts
t11
FPSHIFT2, FPSHIFT pulse width low
2Ts
t12
UD[3:0], LD[3:0] setup to FPSHIFT2 rising, FPSHIFT falling edge
1Ts
t13
UD[3:0], LD[3:0] hold from FPSHIFT2 rising, FPSHIFT falling edge
1Ts
FPFRAME
FPLINE
FPLINE
FPSHIFT
UD[3:0]
LD[3:0]
t9
t1
t2
t4
t3
t6 t7
t11t10
t12 t13
12
t8b
t5b
FPSHIFT2
t8a
t5a
Sync Timing
Data Timing