User`s manual

7: A.C. CHARACTERISTICS
S1D13504 SERIES HARDWARE FUNCTIONAL EPSON 1-29
SPECIFICATION (X19A-A-002-17)
Figure 7-10 Generic Write Bus Asynchronous Timing
Note: 1. If the S1D13504 host interface is disabled, the timing for WAIT# driven low is relative to the falling
edge of CS# or
the first positive edge of BCLK after A[20:0], M/R# becomes valid, whichever one
is later.
Table 7-10 Generic Write Bus Asynchronoud Timing
Symbol Parameter
3.3V
Units
Min. Max.
TBCLK Bus clock period 25 ns
t1
WE0#, WE1# low to CS# low 4 ns
t2
A[20:0], M/R# valid to WE0#, WE1# low 0 ns
t3
WE0#, WE1# high to A[20:0], CS#, M/R# invalid 0 ns
t4
WE0#, WE1# low to D[15:0] valid 20 ns
t5
D[15:0] hold from WE0#, WE1# high 0 ns
t6
1
CS# low to WAIT# driven low 7 ns
t7
WE0#, WE1# high to WAIT# high impedance 6 ns
t5
t4
t2
t7
BCLK
A[20:0]
CS#
WE0#
D[15:0]
WAIT#
t6
Valid
t3
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Valid
WE1#
M/R#
TBCLK
t1