User`s manual

6: INTERFACING TO THE TOSHIBA MIPS TX3912 PROCESSOR
5-50 EPSON APPLICATION NOTES (S19A-G-005-05)
6.3.5 S1D13504 Configuration
The S1D13504 latches MD0 through MD15 to allow selection of the bus mode and other configura-
tion data on the rising edge of RESET#. For details on configuration, refer to the “S1D13504 Hard-
ware Functional Specification”, document number S19A-A-002-xx.
The partial table below only shows those configuration settings relevant to the IT8368E implementa-
tion.
When the S1D13504 is configured for Generic MPU host bus interface, the host interface pins are
mapped as in the table below.
Table 6-5 S1D13504 Configuration using the IT8368E
S1D13504
Pin Name
Value on this pin at rising edge of RESET# is used to configure:
1 (IO VDD) 0 (VSS)
MD0 8-bit host bus interface 16-bit host bus interface
MD[3:1] 011 = Generic MPU host bus interface
MD4 Little Endian Big Endian
MD5 WAIT# is active high (1 = insert wait state) WAIT# is active low (0 = insert wait state)
= configuration for connection using ITE IT8368E.
Table 6-6 S1D13504 Generic MPU Host Bus Interface Pin Mapping
Pin Name Pin Function
WE1# WE1#
BS# Connect to IO V
DD
RD/WR# RD1#
RD# RD0#
WE0# WE0#