User`s manual

6: INTERFACING TO THE TOSHIBA MIPS TX3912 PROCESSOR
5-46 EPSON APPLICATION NOTES (S19A-G-005-05)
6.2.2 Memory Mapping and Aliasing
The S1D13504 requires an addressing space of 2M bytes for the display buffer and 64 bytes for the
registers. This is divided into two address ranges by connecting A23 (demultiplexed from the
TX3912) to the M/R# input of the S1D13504. Using A23 makes this implementation software com-
patible with the two implementations that use the ITE IT8368E (see Section 1.3, “System Design
Using the IT8368E PC Card Buffer” on page 4). All other addresses are ignored.
The S1D13504 address ranges, as seen by the TX3912 on the PC Card slot 1 memory space, are as
follows:
• 6400 0000h: S1D13504 registers aliased 131,072 times at 64 byte intervals over 8M bytes.
• 6480 0000h: S1D13504 display buffer aliased 4 times at 2M byte intervals over 8M bytes.
• 6500 0000h: S1D13504 registers and display buffer, aliased another 3 times over 48M bytes.
Since the TX3912 control signal CARDREG* is ignored, the S1D13504 takes up the entire PC Card
slot 1 configuration space. The address range is software compatible with both ITE IT8368E
implementations.
• 0900 0000h: S1D13504 registers aliased 131,072 times at 64 byte intervals over 8M bytes.
• 0980 0000h: S1D13504 display buffer aliased 4 times at 2M byte intervals over 8M bytes.
Note: If aliasing is undesirable, additional decoding circuitry must be added.
6.2.3 S1D13504 Configuration
The S1D13504 latches MD0 through MD15 to allow selection of the bus mode and other configura-
tion data on the rising edge of RESET#. For details on configuration, refer to the “S1D13504 Hard-
ware Functional Specification”, document number S19A-A-002-xx.
The partial table below shows those configuration settings relevant to the direct connection imple-
mentation.
When the S1D13504 is configured for Generic MPU host bus interface, the host interface pins are
mapped as in the table below.
Table 6-1 S1D13504 Configuration for Direct Connection
S1D13504
Pin Name
Value on this pin at rising edge of RESET# is used to configure:
1 (IO VDD) 0 (VSS)
MD0 8-bit host bus interface
16-bit host bus interface
MD[3:1] 011 = Generic MPU host bus interface
MD4 Little Endian Big Endian
MD5 WAIT# is active high (1 = insert wait state) WAIT# is active low (0 = insert wait state)
= configuration for direct connection with TX3912.
Table 6-2 S1D13504 Generic MPU Host Bus Interface Pin Mapping
Pin Name Pin Function
WE1# WE1#
BS# Connect to IO VDD
RD/WR# RD1#
RD# RD0#
WE0# WE0#