User`s manual

6: INTERFACING TO THE TOSHIBA MIPS TX3912 PROCESSOR
APPLICATION NOTES (S19A-G-005-05) EPSON 5-45
6.2 Direct Connection to the Toshiba TX3912
6.2.1 Hardware Description
The S1D13504 is easily interfaced to the Toshiba TX3912 processor. In the direct connection imple-
mentation, the S1D13504 occupies PC Card slot #1 of the TX3912. Although the address bus of the
TX3912 is multiplexed, it can be demultiplexed using an advanced CMOS latch (e.g., 74ACT373).
The direct connection implementation makes use of the Asynchronous Generic MPU host bus inter-
face capability of the S1D13504.
The following diagram demonstrates a typical implementation of the interface.
Figure 6-1 S1D13504 to TX3912 for Direct Connection
The host interface control signals of the S1D13504 are asynchronous with respect to the S1D13504
bus clock. This gives the system designer full flexibility in choosing the appropriate source (or
sources) for CLKI and BUSCLK. Deciding whether both clocks should be the same and whether to
use DCLKOUT (divided) as the clock source, should be based on the desired:
• pixel and frame rates.
• power budget.
• part count.
• maximum S1D13504 clock frequencies.
The S1D13504 also has internal clock dividers providing additional flexibility.
RD*
WE*
CARD1CSL*
CARD1CSH*
ALE
A[12:0]
D[31:24]
D[23:16]
CARD1WAIT*
DCLKOUT
IO VDD, CORE VDD
RD0#
RD1#
WE0#
WE1#
CS#
M/R#
RESET#
AB[20:13]
AB[12:0]
DB[7:0]
DB[15:8]
WAIT#
BUSCLK
CLKI
TX3912 S1D13504
Latch
Clock
divider
Oscillator
15K pull-up
... or ...
A23
A20:13
V
DD
System RESET
See text
+3.3V
ENDIAN