User`s manual

5: INTERFACING TO THE MOTOROLA MCF5307 MICROPROCESSOR
APPLICATION NOTES (S19A-G-005-05) EPSON 5-37
Figure 5-2 MCF5307 Memory Write Cycle
Burst Cycles
Burst cycles are very similar to normal cycles, except that they occur as a series of four back-to-
back, 32-bit memory reads or writes, with the TIP (Transfer In Progress) output asserted continu-
ously through the burst. Burst memory cycles are mainly intended to facilitate cache line fill from
program or data memory; they are typically not used for transfers to or from IO peripheral devices
such as the S1D13504. The MCF5307 chip selects provide a mechanism to disable burst accesses
for peripheral devices which are not able to support them.
5.2.3 Chip-Select Module
In addition to generating eight independent chip-select outputs, the MCF5307 Chip Select Module
can generate active-low Output Enable (OE) and Write Enable (WE) signals compatible with most
memory and x86-style peripherals. The MCF5307 bus controller also provides a Read/Write (R/W)
signal which is compatible with most 68K peripherals.
Chip selects 0 and 1 can be programmed independently to respond to any base address and block
size. Chip select 0 can be active immediately after reset, and is typically used to control a boot
ROM. Chip select 1 is likewise typically used to control a large static or dynamic RAM block.
Chip selects 2 through 7 have fixed block sizes of 2M bytes each. Each has a unique, fixed offset
from a common, programmable starting address. These chip selects are well-suited to typical I/O
addressing requirements.
Each chip select may be individually programmed for port size (8/16/32 bits), 0-15 wait states or
external acknowledge, address space type, burst or non-burst cycle support, and write protect.
A[31:0]
D[31:0]
SIZ[1:0], TT[1:0]
TS
TA
BCLK0
Wait StatesTransfer Start
R/W
Valid
Transfer Next Transfer
Complete Starts
TIP