User`s manual

4: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR
APPLICATION NOTES (S19A-G-005-05) EPSON 5-33
4.4.4 Test Software
The test software to exercise this interface is very simple. It configures chip select 4 on the MPC821
to map the S1D13504 to an unused 4M byte block of address space; loads the appropriate values
into the option register for CS4; and then writes the value 0 to the S1D13504 register REG[1Bh], to
enable the S1D13504 host interface. At that point the software runs in a tight loop reading the
S1D13504 Revision Code Register REG[00h], which allows monitoring of the bus timing on a logic
analyzer.
The source code for this test routine is as follows:
BR4 equ $120 ; CS4 base register
OR4 equ $124 ; CS4 option register
MemStart equ $40 ; upper word of S1D13504 start address
DisableReg equ $1b ; address of S1D13504 Disable Register
RevCodeReg equ 0 ; address of Revision Code Register
Start mfspr r1,IMMR ; get base address of internal registers
andis. r1,r1,$ffff ; clear lower 16 bits to 0
andis. r2,r0,0 ; clear r2
oris r2,r2,MemStart ; write base address
ori r2,r2,$0801 ; port size 16 bits; select GPCM; enable
stw r2,BR4(r1) ; write value to base register
andis. r2,r0,0 ; clear r2
oris r2,r2,$ffc0 ; address mask – use upper 10 bits
ori r2,r2,$0708 ; normal CS negation; delay CS 1/2 clock;
; inhibit burst
stw r2,OR4(r1) ; write to option register
andis. r1,r0,0 ; clear r1
oris r1,r1,MemStart ; point r1 to start of SED1354 mem space
stb r1,DisableReg(r1) ; write 0 to disable register
Loop lbz r0,RevCodeReg(r1) ; read revision code into r1
b Loop ; branch forever
end
This code was entered into the memory of the MPC821ADS using the line-by-line assembler in
MPC8BUG, the debugger provided with the ADS board.
1
It was executed on the ADS and a logic
analyzer was used to verify operation of the interface hardware.
It is important to note that when the MPC821 comes out of reset, its on-chip caches and MMU are
disabled. If the data cache is enabled, then the MMU must be set up so that the S1D13504 memory
block is tagged as non-cacheable, to ensure that accesses to the S1D13504 will occur in proper
order, and also to ensure that the MPC821 does not attempt to cache any data read from or written to
the S1D13504 or its display refresh buffer.
1. MPC8BUG does not support comments or symbolic equates; these have been added for clarity.