User`s manual

5: PIN OUT
1-14 EPSON S1D13504 SERIES HARDWARE FUNCTIONAL
SPECIFICATION (X19A-A-002-17)
*1: When configured as IO pins.
5.4.6 Miscellaneous
∗1: When configured as IO pin. Output may be 1 or 0.
DACRS0 I/O 100 114 C/TS1 Hi-Z /
Output 0
(∗1)
This pin has multiple functions.
• Register Select bit 0 for external RAMDAC support.
• General Purpose IO (GPIO8).
See Table 5-11, “LCD, CRT, RAMDAC Interface Pin Mapping,”
on page 17.
DACP0 I/O 98 112 C/CN3 Hi-Z /
Output 0
(∗1)
This pin has multiple functions.
• Pixel Data bit 0 for external RAMDAC support.
• General Purpose IO (GPIO6).
See Table 5-11, “LCD, CRT, RAMDAC Interface Pin Mapping,”
on page 17.
HRTC I/O 102 116 C/CN3 Hi-Z /
Output 0
(∗1)
This pin has multiple functions.
• Horizontal Retrace signal for CRT.
• General Purpose IO (GPIO10).
See Table 5-11, “LCD, CRT, RAMDAC Interface Pin Mapping,”
on page 17.
VRTC I/O 103 117 C/CN3 Hi-Z /
Output 0
(∗1)
This pin has multiple functions.
• Vertical Retrace signal for CRT.
• General Purpose IO (GPIO11).
See Table 5-11, “LCD, CRT, RAMDAC Interface Pin Mapping,”
on page 17.
BLANK# I/O 85 95 C/CN3 Hi-Z /
Output 0
(∗1)
This pin has multiple functions.
• Blanking signal for DAC.
• General Purpose IO (GPIO5).
See Table 5-11, “LCD, CRT, RAMDAC Interface Pin Mapping,”
on page 17.
DACCLK O 86 96 C/CN3 Output 0 Pixel Clock for RAMDAC.
Table 5-6 Miscellaneous Pin Descriptions
Pin Names Type
Pin #
Driver
Reset
= 0 Value
DescriptionF00A,
F01A
F02A
SUSPEND# I/O 106 120 CS/TS1 Hi-Z /
Output
(∗1)
This pin has multiple functions.
• When MD9 = 0 at rising edge of RESET#, this pin is an active-
low input used to place the S1D13504 into suspend mode; see
Section 13, “Power Save Modes” on page 99 for details.
• When MD[10:9] = 01 at rising edge of RESET#, this pin is an
output with a reset state of 0. Its state is controlled by
REG[21h] bit 7.
• When MD[10:9] = 11 at rising edge of RESET#, this pin is an
output with a reset state of 1. Its state is controlled by
REG[21h] bit 7.
GPIO0 I/O 12 14 C/TS1 Hi-Z General Purpose IO pin 0.
TSTEN I 107 121 CD Hi-Z
(pulled 0)
Test Enable. This in should be connected to V
SS for normal oper-
ation.
NC – – 1, 2
35–38
71–74
107–110
143, 144
– – No connect
Table 5-5 CRT and RAMDAC Interface Pin Descriptions
Pin Names Type
Pin #
Driver
Reset
= 0 Value
DescriptionF00A,
F01A
F02A