User`s manual

4: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR
APPLICATION NOTES (S19A-G-005-05) EPSON 5-23
4.2 Interfacing to the MPC821
4.2.1 The MPC8xx System Bus
The MPC8xx family of processors feature a high-speed synchronous system bus typical of modern
RISC microprocessors. This section is an overview of the operation of the CPU bus to establish
interface requirements.
4.2.2 Overview
The MPC8xx microprocessor family uses a synchronous address and data bus. All outputs and
inputs are timed with respect to a square-wave reference clock called MCLK (Master Clock). This
clock runs at the machine cycle speed of the CPU core, typically 25 to 50 MHz
1
. Most outputs from
the processor change state on the rising edge of this clock; similarly, most inputs to the processor are
sampled on the rising edge.
It should be noted that all Power PC microprocessors, including the MPC8xx family, use bit notation
that is reversed from the convention used in most other microprocessor systems. Bit numbering
always starts at zero with the most significant bit, and increments in value to the least-significant bit.
This means that the most significant bits of the address bus and data bus are A0 and D0, respectively,
while the least significant bits are A31 and D31, respectively.
Both the address and the data bus are 32 bits in width. A parity bit is supported for each of the four
byte lanes on the data bus. Parity checking is done when data is read from external memory or
peripherals, and generated by the MPC8xx bus controller on write cycles. All IO accesses are mem-
ory-mapped; there is no separate IO space in the Power PC architecture.
Support is provided for alternate bus masters, both on-chip (DMA controllers) and off-chip (other
processors and peripheral controllers). For more detail on this topic, please refer to the literature ref-
erenced at the end of this document.
The bus can support two types of cycle, normal and burst. Burst memory cycles are used to fill on-
chip cache memories, and for certain on-chip DMA operations. Normal cycles are used for all other
data transfers.
1. An option in the clock control register allows the external bus to run at one-half the CPU core speed; this is
typically used when the CPU core is operated above 50 MHz.