User`s manual

5: PIN OUT
S1D13504 SERIES HARDWARE FUNCTIONAL EPSON 1-13
SPECIFICATION (X19A-A-002-17)
5.4.3 LCD Interface
∗1: Output may be 1 or 0.
5.4.4 Clock Input
5.4.5 CRT and External RAMDAC Interface
Table 5-3 LCD Interface Pin Descriptions
Pin Names Type
Pin #
Driver
Reset
= 0 Value
DescriptionF00A,
F01A
F02A
FPDAT[8:0] O 88
82–75
98
92–85
CN3 Output 0 Panel Data
FPDAT[15:9] O 95–89 105–99 CN3 Output 0 These pins have multiple functions.
• Panel Data for 16-bit panels .
• Pixel Data for external RAMDAC support.
See Table 5-11, “LCD, CRT, RAMDAC Interface Pin Mapping,”
on page 17.
FPFRAME O 69 79 CN3 Output 0 Frame Pulse
FPLINE O 70 80 CN3 Output 0 Line Pulse
FPSHIFT O 73 83 CN3 Output 0 Shift Clock Pulse
LCDPWR O 71 81 CO1 Output
(∗1)
LCD power control output. The active polarity of this output is
selected by the state of MD10 at the rising edge of RESET# - see
Section 5.5, “Summary of Configuration Options” on page 16.
This output is controlled by the power save mode circuitry - see
Section 13, “Power Save Modes” on page 99 for details.
DRDY O 72 82 CN3 Output 0 This pin has multiple functions which are automatically selected
depending on panel type used.
• For TFT panels, this is the display enable output (DRDY).
• For passive LCDs with Format 1 interfaces, this is the 2nd Shift
Clock (FPSHIFT2).
• For all other LCD panels, this is the LCD backplane bias signal
(MOD).
See Table 5-11, “LCD, CRT, RAMDAC Interface Pin Mapping,”
on page 17 and REG[02h] for details.
Table 5-4 Clock Input Pin Description
Pin Names Type
Pin #
Driver
Reset
= 0 Value
DescriptionF00A,
F01A
F02A
CLKI I 105 119 C Hi-Z Input clock for the internal pixel clock (PCLK) and memory
clock (MCLK). PCLK and MCLK are derived from CLKI – see
REG[19h] for details.
Table 5-5 CRT and RAMDAC Interface Pin Descriptions
Pin Names Type
Pin #
Driver
Reset
= 0 Value
DescriptionF00A,
F01A
F02A
DACRD# I/O 84 94 C/TS1 Hi-Z /
Output 1
(∗1)
This pin has multiple functions.
• Read signal for external RAMDAC support.
• General Purpose IO (GPIO4).
See Table 5-11, “LCD, CRT, RAMDAC Interface Pin Mapping,”
on page 17.
DACWR# I/O 99 113 C/TS1 Hi-Z /
Output 1
(∗1)
This pin has multiple functions.
• Write signal for external RAMDAC support.
• General Purpose IO (GPIO7).
See Table 5-11, “LCD, CRT, RAMDAC Interface Pin Mapping,”
on page 17.
DACRS1 I/O 101 115 C/TS1 Hi-Z /
Output 0
(∗1)
This pin has multiple functions.
• Register Select bit 1 for external RAMDAC support.
• General Purpose IO (GPIO9).
See Table 5-11, “LCD, CRT, RAMDAC Interface Pin Mapping,”
on page 17.