User`s manual

3: INTERFACING TO THE PC CARD BUS
5-18 EPSON APPLICATION NOTES (S19A-G-005-05)
3.4.2 S1D13504 Hardware Configuration
The S1D13504 uses MD15 through MD0 to allow selection of the bus mode and other configuration
data on the rising edge of RESET#. Refer to the “S1D13504 Hardware Functional Specification”,
document number S19A-A-002-xx for details.
The tables below show only those configuration settings important to the PC Card host bus interface.
3.4.3 PAL Equations
The PAL equations used for the implementation presented in this document are as follows. Note that
PALASM syntax uses positive logic. Active low pins are inverted in the pin declaration section.
CHIP PCCAPP PAL16L8
PIN 1 /oe COMBINATORIAL ; bus read enable
PIN 2 /we COMBINATORIAL ; bus write enable
PIN 3 /ce1 COMBINATORIAL ; bus low byte enable
PIN 4 /ce2 COMBINATORIAL ; bus high byte enable
PIN 5 /pcreg COMBINATORIAL ; bus CIS cycle enable
PIN 6 breset COMBINATORIAL ; bus reset (active high)
PIN 12 /we0 COMBINATORIAL ; SED1354 low byte write
PIN 13 /we1 COMBINATORIAL ; SED1354 high byte write
PIN 14 /cs COMBINATORIAL ; SED1354 chip select
PIN 15 /rd0 COMBINATORIAL ; SED1354 low byte read
PIN 16 /rd1 COMBINATORIAL ; SED1354 high byte read
PIN 17 /reset COMBINATORIAL ; SED1354 reset
PIN 10 gnd ; supply
PIN 20 vcc ; supply
EQUATIONS
rd0 = oe * ce1 * /pcreg ; /pcreg means disable in attribute mode
rd1 = oe * ce2 * /pcreg ; /pcreg means disable in attribute mode
we0 = we * ce1 * /pcreg ; /pcreg means disable in attribute mode
we1 = we * ce2 * /pcreg ; /pcreg means disable in attribute mode
cs = rd0 + rd1 + we0 + we1
reset = breset ; inversion appears in pin declaration
; section
Table 3-2 Summary of Power-On/Reset Options
S1D13504
Pin Name
Value on this pin at rising edge of RESET# is used to configure:(1/0)
10
MD0 8-bit host bus interface
16-bit host bus interface
MD1
For host bus interface selection see Table 3-3 “Host Bus Interface Selection”MD2
MD3
MD4 Little Endian Big Endian
MD5 WAIT# is active high (1 = insert wait state) WAIT# is active low (0 = insert wait state)
= configuration for PC Card host bus interface
Table 3-3 Host Bus Interface Selection
MD3 MD2 MD1 Host Bus Interface
0 0 0 SH-3
0 0 1 MC68K Bus 1 (e.g. MC68000)
0 1 0 MC68K Bus 2 (e.g. MC68030)
0 1 1 Generic MPU
1 ×× Reserved
= configuration for PC Card host bus interface