User`s manual

5: PIN OUT
1-12 EPSON S1D13504 SERIES HARDWARE FUNCTIONAL
SPECIFICATION (X19A-A-002-17)
5.4.2 Memory Interface
*1: When configured as IO pins.
Table 5-2 Memory Interface Pin Descriptions
Pin Names Type
Pin #
Driver
Reset
= 0 Value
DescriptionF00A,
F01A
F02A
LCAS# O 50 56 CO1 Output 1 This pin has multiple functions.
• For dual CAS# DRAM, this is the column address strobe for
the lower byte (LCAS#).
• For single CAS# DRAM, this is the column address strobe
(CAS#).
See Table 5-10, “Memory Interface Pin Mapping,” on page 16
for summary.
UCAS# O 49 55 CO1 Output 1 This pin has multiple functions.
• For dual CAS# DRAM, this is the column address strobe for
the upper byte (UCAS#).
• For single CAS# DRAM, this is the write enable signal for the
upper byte (UWE#).
See Table 5-10, “Memory Interface Pin Mapping,” on page 16
for summary.
WE# O 48 54 CO1 Output 1 This pin has multiple functions.
• For dual CAS# DRAM, this is the write enable signal (WE#).
• For single CAS# DRAM, this is the write enable signal for the
lower byte (LWE#).
See Table 5-10, “Memory Interface Pin Mapping,” on page 16
for summary.
RAS# O 47 53 CO1 Output 1 Row address strobe.
MD[15:0] I/O 67, 65
63, 61
59, 57
55, 53
52, 54
56, 58
60, 62
64, 66
76, 70
68, 66
64, 62
60, 58
59, 61
63, 65
67, 69
75, 77
CD2/TS1 Hi-Z
(pulled 0)
These pins have multiple functions.
• Bi-directional memory data bus.
• During reset, these pins are inputs and their states at the rising
edge of RESET# are used to configure the chip. Internal pull-
down resistors (typical values of 100KΩ/100KΩ/120KΩ at
5.0V/3.3V/3.0V respectively) pull the reset states to 0. External
pull-up resistors can be used to pull the reset states to 1. See
Section 5.5, “Summary of Configuration Options” on page 16.
MA[8:0] O 43, 41
39, 37
35, 34
36, 38
40
46, 44
42, 40
41, 43
45, 47
49
CO1 Output 0 Multiplexed memory address.
MA9 I/O 45 51 C/TS1 Hi-Z /
Output 0
(∗1)
This pin has multiple functions.
• For 2M byte DRAM, this is memory address bit 9 (MA9).
• For asymmetrical 512K byte DRAM, this is memory address
bit 9 (MA9).
• For symmetrical 512K byte DRAM, this pin can be used as
general purpose IO (GPIO3).
See Table 5-10, “Memory Interface Pin Mapping,” on page 16
for summary.
MA10 I/O 42 48 C/TS1 Hi-Z /
Output 0
(∗1)
This pin has multiple functions.
• For asymmetrical 2M byte DRAM, this is memory address bit
10 (MA10).
• For symmetrical 2M byte DRAM and all 512K byte DRAM,
this pin can be used as general purpose IO (GPIO1).
See Table 5-10, “Memory Interface Pin Mapping,” on page 16
for summary.
MA11 I/O 44 50 C/TS1 Hi-Z /
Output 0
(∗1)
This pin has multiple functions.
• For asymmetrical 2M byte DRAM, this is memory address bit
11 (MA11).
• For symmetrical 2M byte DRAM and all 512K byte DRAM,
this pin can be used as general purpose IO (GPIO2).
See Table 5-10, “Memory Interface Pin Mapping,” on page 16
for summary.