User`s manual

2: INTERFACING TO THE NEC VR4102TM MICROPROCESSOR
5-10 EPSON APPLICATION NOTES (S19A-G-005-05)
2.2 Hardware Description
2.2.1 S1D13504 Configuration
The S1D13504 is configured on power-up by latching the power-on state of the DRAM data pins,
MD[15:0]. Refer to the “S1D13504 Hardware Functional Specification”, document number S19A-
A-002-xx for details.
The “partial” table below only shows those configuration settings important to this specific CPU
interface.
2.2.2 NEC VR4102
TM
Configuration
The NEC VR4102
TM
provides the internal address decoding necessary to map to an external LCD
controller. Physical address 0x0A000000h to 0x0AFFFFFFh (16M bytes) is reserved for an external
LCD controller.
The S1D13504 supports up to 2M bytes of display buffer. The NEC VR4102
TM
address line A21 is
used to select between the S1D13504 display buffer and internal register set.
The VR4102
TM
uses a read, write and system high-byte enable to interface to an external LCD con-
troller. The S1D13504 uses low and high byte read and write strobes and therefore minimal “glue”
logic is necessary.
Table 2-1 Summary of Power On / Reset Options
S1D13504
Pin Name
Value on this pin at rising edge of RESET# is used to configure:(1/0)
10
MD0 8-bit host bus interface 16-bit host bus interface
MD[3:1] 011 = Generic bus interface
MD4 Little Endian Big Endian
MD5 WAIT# is active high (1 = insert wait state) WAIT# is active low (0 = insert wait state)
Table 2-2 NEC / S1D13504 Truth Table
NEC Signals
Cycle S1D13504 Signals
SHB# RD# WR# A0
10108-bit even address Read RD0# = low
RD1# = high
10118-bit odd address Read RD0# = high
RD1# - low
001x 16-bit Read RD0# = low
RD1# - low
11008-bit even address Write WR0# = low
WR1# = high
11018-bit odd address Write WR0# = high
WR1# = low
010x 16-bit Write WR0# = low
WR1# = low