User`s manual

5: PIN OUT
S1D13504 SERIES HARDWARE FUNCTIONAL EPSON 1-11
SPECIFICATION (X19A-A-002-17)
BUSCLK I 108 122 C Hi-Z System bus clock. See Table 5-9, “Host Bus Interface Pin Map-
ping,” on page 16.
BS# I 6 8 CS Hi-Z This pin has multiple functions.
• For SH-3 mode, this pin inputs the bus start signal (BS#).
• For MC68K Bus 1, this pin inputs the address strobe (AS#).
• For MC68K Bus 2, this pin inputs the address strobe (AS#).
• For Generic Bus, this pin must be tied to IO VDD.
See Table 5-9, “Host Bus Interface Pin Mapping,” on page 16.
RD/WR# I 10 12 CS Hi-Z This pin has multiple functions.
• For SH-3 mode, this pin inputs the RD/WR# signal. The
S1D13504 needs this signal for early decode of the bus cycle.
• For MC68K Bus 1, this pin inputs the R/W# signal.
• For MC68K Bus 2, this pin inputs the R/W# signal.
• For Generic Bus, this pin inputs the read command for the
upper data byte (RD1#).
See Table 5-9, “Host Bus Interface Pin Mapping,” on page 16.
RD# I 7 9 CS Hi-Z This pin has multiple functions.
• For SH-3 mode, this pin inputs the read signal (RD#).
• For MC68K Bus 1, this pin must be tied to IO V
DD.
• For MC68K Bus 2, this pin inputs the bus size bit 1 (SIZ1).
• For Generic Bus, this pin inputs the read command for the
lower data byte (RD0#).
See Table 5-9, “Host Bus Interface Pin Mapping,” on page 16.
WE0# I 8 10 CS Hi-Z This pin has multiple functions.
• For SH-3 mode, this pin inputs the write enable signal for the
lower data byte (WE0#).
• For MC68K Bus 1, this pin must be tied to IO VDD.
• For MC68K Bus 2, this pin inputs the bus size bit 0 (SIZ0).
• For Generic Bus, this pin inputs the write enable signal for the
lower data byte (WE0#).
See Table 5-9, “Host Bus Interface Pin Mapping,” on page 16.
WAIT# O 13 15 TS2 Hi-Z The active polarity of the WAIT# output is configurable on the
rising edge of RESET# - see Section 5.5, “Summary of Configu-
ration Options” on page 16.
This pin has multiple functions.
• For SH-3 mode, this pin outputs the wait request signal
(WAIT#); MD5 must be pulled low during reset by the internal
pull-down resistor.
• For MC68K Bus 1, this pin outputs the data transfer acknowl-
edge signal (DTACK#); MD5 must be pulled high during reset
by an external pull-up resistor.
• For MC68K Bus 2, this pin outputs the data transfer and size
acknowledge bit 1 (DSACK1#); MD5 must be pulled high dur-
ing reset by an external pull-up resistor.
• For Generic Bus, this pin outputs the wait signal (WAIT#);
MD5 must be pulled low during reset by the internal pull-down
resistor.
See Table 5-9, “Host Bus Interface Pin Mapping,” on page 16.
RESET# I 11 13 CS Input 0 Active low input to clear all internal registers and to force all sig-
nals to their inactive states.
Table 5-1 Host Interface Pin Descriptions
Pin Names Type
Pin #
Driver
Reset
= 0 Value
DescriptionF00A,
F01A
F02A