User`s manual

6: CRT CONSIDERATIONS
S1D13504 PROGRAMMING NOTES EPSON 2-23
AND EXAMPLES (S19A-G-002-06)
6 CRT CONSIDERATIONS
6.1 Introduction
The CRT timing is based on both the “VESA Monitor Timing Standards Version 1.0” and “Clock-
ing” (Chapter 11) in the “S1D13504 Hardware Functional Specification”. The following sections
describe CRT considerations.
6.1.1 CRT Only
For CRT only, the Dual/Single Panel Select bit of Panel Type Register (REG[02h]) must first be set
to single passive LCD panel. The monitor configuration registers then need to be set to follow the
VESA timing standard.
Note: If only the CRT is used, it is also useful to disable the LCD power (set REG[1Ah] bit 4 = 1). This will
reduce power consumption.
To program the external RAMDAC, set the CRT Enable bit in the Display Mode Register
(REG[0Dh]) to 1. Once the CRT is enabled, the GPIO registers will be automatically set to access
the external RAMDAC. Next, program the RAMDAC Write Mode Address register and the RAM-
DAC Palette Data register as desired (refer to sample code in Section 9.1 for details).
When programming the RAMDAC control registers, connect the RAMDAC to the low-byte of the
CPU data bus for Little-Endian and the high-byte for Big-Endian. The RAMDAC registers are
mapped as follows:
Note: When accessing the External RAMDAC Control registers with either of the Little-Endian or Big-Endi-
an architectures described above, accessing the adjacent unused registers is prohibited.
Table 6-2 shows some example register data for setting up CRT only mode for certain combinations
of resolutions, frame rates and pixel clocks. All the examples in this chapter are assumed to be for a
Little-Endian system, 8 bpp color depth and 2M bytes of 60ns EDO-DRAM.
Table 6-1 RAMDAC Register Mapping for Little/Big-Endian
Register Name Little-Endian Big-Endian
RAMDAC Pixel Read Mask REG[28h] REG[29h]
RAMDAC Read Mode Address REG[2Ah] REG[2Bh]
RAMDAC Write Mode Address REG[2Ch] REG[2Dh]
RAMDAC Palette Data REG[2Eh] REG[2Fh]
Table 6-2 Related Register Data for CRT Only
Register
640X480@60Hz
PCLK=25.175MHz
640X480@75Hz
PCLK=31.500MHz
800X600@56Hz
PCLK=36.0MHz
800X600@60Hz
PCLK=40.0MHz
Notes
REG[04h] 0100 1111 0100 1111 0110 0011 0110 0011 set horizontal display width
REG[05h] 0001 0011 0001 1000 0001 1011 0001 1111 set horizontal non-display period
REG[06h] 0000 0001 0000 0001 0000 0010 0000 0100 set HSYNC start position
REG[07h] 0000 1011 0000 0111 1000 1000 1000 1111 set HSYNC polarity and pulse width
REG[08h] 1101 1111 1101 1111 0101 0111 0101 0111 set vertical display height bits 7–0
REG[09h] 0000 0001 0000 0001 0000 0010 0000 0010 set vertical display height bits 9–8
REG[0Ah] 0010 1100 0001 0011 0001 1000 0001 1011 set vertical non-display period
REG[0Bh] 0000 1001 0000 0000 0000 0000 0000 0000 set VSYNC start position
REG[0Ch] 0000 0001 0000 0010 1000 0001 1000 0011 set VSYNC polarity and pulse width
REG[0Dh] 0000 1110 0000 1110 0000 1110 0000 1110 set 8 bpp and CRT enable
REG[19h] 0000 0000 0000 0000 0000 0000 0000 0000 set MCLK and PCLK divide
REG[2Ch] 0000 0000 0000 0000 0000 0000 0000 0000 set write mode address to 0
REG[2Eh] load RAMDAC palette data