User`s manual

3: DISPLAY BUFFER
2-8 EPSON S1D13504 PROGRAMMING NOTES
AND EXAMPLES (S19A-G-002-06)
3.3 Look-Up Table (LUT)
This section provides a description of the LUT registers, followed by a description of the color and
gray shade LUTs and a discussion of the banks available in the 2 and 8 bit-per-pixel (bpp) modes.
The S1D13504 LUT is only used for the panel interface. The optional RAMDAC is used to deter-
mine the colors for the CRT. See Section 6, “CRT Considerations” on page 23.
3.3.1 Look-Up Table Registers
The S1D13504 LUT Registers are located at offsets 24h, 26h and 27h. They consist of a LUT
address register, data register and bank register. Refer to the “S1D13504 Hardware Functional
Specification”, document number S19A-A-002-xx for more details.
RGB Index
Selects which LUT to program. If set for Auto-increment, it will start at the Red LUT of the Index
selected. Then with consecutive writes/reads it will increment to Green, then Blue of the same index,
it will then increment the index and start at the Red LUT again.
Auto-increment algorithm:
1. Set RGB Index to 0 for Auto-increment, set LUT address to 0 (i.e. REG[24h]=00h).
2. While count < or = to (16*3), write data byte to REG[26h].
R, G or B Index select algorithm:
1. Set RGB Index to R(01b), G(10b), or B(11b), set LUT address to 0 (e.g. REG[24h]=10h).
2. While count < or = 16, write data byte to REG[26h], increment LUT address.
LUT Address
Selects start index of the LUT in which to read data from, or write data to. Bank select has no effect
on the CPU read/write to the LUT.
LUT Data
4-bit data value to write.
Bank Select Bits
LUT banks are provided to give the application developer a choice of colors/gray shades. While the
chosen color depth (bpp) may limit the simultaneous colors available, the panel is capable of storing
different combinations of colors in banks. This is useful when an application developer chooses to
set Bank 0 to low intensity colors and set Bank 1 to high intensity. The application can easily switch
between low intensity output and high intensity output by using one register write.
Only two display modes support these bits: 2 bpp and 8 bpp. All other modes either bypass the LUT
or have only Bank 0 starting at Index 00h.
In 2 bpp mode, the 16 entry LUTs are logically split into 4 groups of 4 entries for each of R, G, B.
Bank 0 = Indexes 00–03h
Bank 1 = Indexes 04–07h
Bank 2 = Indexes 08–0Bh
Bank 3 = Indexes 0C–0Fh
REG[24h] Look-Up Table Address Register Read/Write
n/a n/a
RGB Index
Bit 1
RGB Index
Bit 0
LUT Address
Bit 3
LUT Address
Bit 2
LUT Address
Bit 1
LUT Address
Bit 0
REG[26h] Look-Up Table Data Register Read/Write
n/a n/a n/a n/a
LUT Data
Bit 3
LUT Data
Bit 2
LUT Data
Bit 1
LUT Data
Bit 0
REG[27h] Look-Up Table Bank Register Read/Write
n/a n/a
Red Bank
Select Bit 1
Red Bank
Select Bit 0
Blue Bank
Select Bit 1
Blue Bank
Select Bit 0
Green Bank
Select Bit 1
Green Bank
Select Bit 0