User`s manual

2: PROGRAMMING THE S1D13504 REGISTERS
S1D13504 PROGRAMMING NOTES
EPSON
2-5
AND EXAMPLES (S19A-G-002-06)
2.3 Disabling the Half Frame Buffer Sequence
The Half Frame Buffer can be ENABLED asynchronously.
To DISABLE the Half Frame Buffer, do the following:
1. Disable the display FIFO REG[23] bit 7 = 1.
2. Set the horizontal resolution to 0 (REG[04] = 0).
Setting the horizontal resolution = 0 will shut-off any Half Frame Buffer DRAM accesses within
1024 PCLK's or less (1024 PCLK’s is the worst case).
3. Wait for VNDP 1 → 0 → 1 transitions (REG[0A] bit 7).
Waiting for 1 FRAME delay will guarantee that the Half Frame Buffer is idle.
4. Disable the Half Frame Buffer (REG[1B] bit 0 = 1).
5. Re-program the horizontal resolution to your original value.