User`s manual

CONTENTS
S1D13504 PROGRAMMING NOTES
EPSON
2-i
AND EXAMPLES (S19A-G-002-06)
Contents
Table of Contents
1I NTRODUCTION .........................................................................................................................2-1
2P ROGRAMMING THE S1D13504 R EGISTERS ...............................................................................2-2
2.1 Registers Requiring Special Consideration...................................................................................2-2
2.1.1 REG[01] bit 0 - Memory Type ..........................................................................................2-2
2.1.2 REG[22] bits 7–2 - Performance Enhancement Register 0 .............................................2-2
2.1.3 REG[02] bit 1 - Dual/Single Panel Type ..........................................................................2-2
2.1.4 REG[1B] bit 0 - Half Frame Buffer Disable ......................................................................2-2
2.1.5 REG[23] Display FIFO .....................................................................................................2-2
2.2 Register Initialization .....................................................................................................................2-3
2.2.1 Initialization Sequence.....................................................................................................2-3
2.2.2 Initialization Example .......................................................................................................2-3
2.2.3 Re-Programming Registers .............................................................................................2-4
2.3 Disabling the Half Frame Buffer Sequence ...................................................................................2-5
3D ISPLAY B UFFER .....................................................................................................................2-6
3.1 Display Buffer Location .................................................................................................................2-6
3.2 Display Buffer Organization...........................................................................................................2-6
3.2.1 Memory Organization for One Bit-per-pixel (2 Colors/Gray Shades)...............................2-6
3.2.2 Memory Organization for Two Bit-per-pixel (4 Colors/Gray Shades)...............................2-6
3.2.3 Memory Organization for Four Bit-per-pixel (16 Colors/Gray Shades)............................2-6
3.2.4 Memory Organization for Eight Bit-per-pixel (256 Colors) ...............................................2-7
3.2.5 Memory Organization for 15 Bit-per-pixel (32768 Colors) ...............................................2-7
3.2.6 Memory Organization for 16 Bit-per-pixel (65536 Colors) ...............................................2-7
3.3 Look-Up Table (LUT).....................................................................................................................2-8
3.3.1 Look-Up Table Registers .................................................................................................2-8
3.3.2 Look-Up Table Organization............................................................................................2-9
4A DVANCED T ECHNIQUES .........................................................................................................2-13
4.1 Virtual Display .............................................................................................................................2-13
4.1.1 Registers........................................................................................................................2-13
4.1.2 Examples .......................................................................................................................2-14
4.2 Panning and Scrolling .................................................................................................................2-15
4.2.1 Registers........................................................................................................................2-16
4.2.2 Examples .......................................................................................................................2-17
4.3 Split Screen .................................................................................................................................2-18
4.3.1 Registers........................................................................................................................2-18
4.3.2 Examples .......................................................................................................................2-19
5 LCD P OWER S EQUENCING AND P OWER S AVE M ODES ..............................................................2-20
5.1 Introduction to LCD Power Sequencing ......................................................................................2-20
5.2 Introduction to Power Save Modes .............................................................................................2-20
5.3 Registers .....................................................................................................................................2-20
5.4 Suspend Sequencing ..................................................................................................................2-21
5.4.1 Suspend Enable Sequence ...........................................................................................2-21
5.4.2 Suspend Disable Sequence ..........................................................................................2-21
5.5 LCD Enable/Disable Sequencing (REG[0D] bit 0) ......................................................................2-22
6 CRT C ONSIDERATIONS ...........................................................................................................2-23
6.1 Introduction..................................................................................................................................2-23
6.1.1 CRT Only .......................................................................................................................2-23
6.1.2 Simultaneous Display ....................................................................................................2-24
7I DENTIFYING THE S1D13504 ..................................................................................................2-26
8H ARDWARE A BSTRACTION L AYER (HAL).................................................................................2-27
8.1 Introduction..................................................................................................................................2-27