User`s manual

CONTENTS
S1D13504 SERIES HARDWARE FUNCTIONAL
EPSON
1-v
SPECIFICATION (X19A-A-002-17)
Figure 7-41 Dual Color 16-Bit Panel A.C. Timing ..................................................................................1-58
Figure 7-42 16-Bit TFT Panel Timing ....................................................................................................1-59
Figure 7-43 TFT A.C. Timing .................................................................................................................1-60
Figure 7-44 CRT Timing ........................................................................................................................1-61
Figure 7-45 CRT A.C. Timing ................................................................................................................1-62
Figure 7-46 Generic Bus RAMDAC Read / Write Timing ......................................................................1-63
Figure 9-1 Display Buffer Addressing..................................................................................................1-86
Figure 10-1 1/2/4/8 Bit-Per-Pixel Format Memory Organization............................................................1-88
Figure 10-2 15/16 Bit-Per-Pixel Format Memory Organization..............................................................1-89
Figure 10-3 Image Manipulation............................................................................................................1-90
Figure 12-1 1 Bit-Per-Pixel – 2-Level Gray-Shade Mode Look-Up Table Architecture .........................1-94
Figure 12-2 2 Bit-Per-Pixel – 4-Level Gray-Shade Mode Look-Up Table Architecture .........................1-94
Figure 12-3 4 Bit-Per-Pixel – 16-Level Gray-Shade Mode Look-Up Table Architecture .......................1-95
Figure 12-4 1 Bit-Per-Pixel – 2-Level Color Look-Up Table Architecture ..............................................1-95
Figure 12-5 2 Bit-Per-Pixel – 4-Level Color Mode Look-Up Table Architecture ....................................1-96
Figure 12-6 4 Bit-Per-Pixel – 16-Level Color Mode Look-Up Table Architecture ..................................1-97
Figure 12-7 8 Bit-Per-Pixel – 256-Level Color Mode Look-Up Table Architecture ................................1-98
Figure 14-1 Mechanical Drawing QFP15-128pin.................................................................................1-101
Figure 14-2 Mechanical Drawing TQFP15-128pin ..............................................................................1-102
Figure 14-3 Mechanical Drawing QFP20-144pin.................................................................................1-103
List of Tables
Table 2-1 S1D13504 Series Package List............................................................................................1-3
Table 5-1 Host Interface Pin Descriptions..........................................................................................1-10
Table 5-2 Memory Interface Pin Descriptions ....................................................................................1-12
Table 5-3 LCD Interface Pin Descriptions ..........................................................................................1-13
Table 5-4 Clock Input Pin Description ................................................................................................1-13
Table 5-5 CRT and RAMDAC Interface Pin Descriptions ..................................................................1-13
Table 5-6 Miscellaneous Pin Descriptions..........................................................................................1-14
Table 5-7 Power Supply Pin Descriptions ..........................................................................................1-15
Table 5-8 Summary of Power On / Reset Options .............................................................................1-16
Table 5-9 Host Bus Interface Pin Mapping.........................................................................................1-16
Table 5-10 Memory Interface Pin Mapping ..........................................................................................1-16
Table 5-11 LCD, CRT, RAMDAC Interface Pin Mapping .....................................................................1-17
Table 6-1 Absolute Maximum Ratings................................................................................................1-18
Table 6-2 Recommended Operating Conditions ................................................................................1-18
Table 6-3 Input Specifications ............................................................................................................1-18
Table 6-4 Output Specifications .........................................................................................................1-18
Table 7-1 SH-3 Interface Timing ........................................................................................................1-20
Table 7-2 SH-3 Write Bus Timing.......................................................................................................1-21
Table 7-3 MC68000 Bus 1 InterfaceTiming........................................................................................1-22
Table 7-4 MC68000 Read Bus Timing ...............................................................................................1-23
Table 7-5 MC68030 Bus 2 Interface Timing.......................................................................................1-24
Table 7-6 MC68030 Read Bus Timing ...............................................................................................1-25
Table 7-7 Generic MPU Interface Synchronous Timing.....................................................................1-26
Table 7-8 Generic Write Bus Synchronous Timing ............................................................................1-27
Table 7-9 Generic MPU Interface Asynchronous Timing ...................................................................1-28
Table 7-10 Generic Write Bus Asynchronoud Timing ..........................................................................1-29
Table 7-11 Clock Input Requirements..................................................................................................1-30
Table 7-12 EDO DRAM Read Timing...................................................................................................1-31
Table 7-13 EDO DRAM Write Timing...................................................................................................1-32