Specifications

I-68 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)
Table 4.9.1 shows the control bits and their addresses for
the SVD circuit and the heavy load protection function.
Table 4.9.1 Control bits for SVD circuit and heavy load protection function
Control of SVD cir-
cuit and heavy load
protection function
Heavy load protection mode on/off (0FAH D3)
When 1 is written: Heavy load protection mode on
When 0 is written: Heavy load protection mode off
Reading: Valid
When HLMOD is set to 1, the IC enters the heavy load
protection mode, and sampling control is executed for the
time the SVD circuit is on. The sampling timing is as fol-
lows:
Sampling in cycles of 2 Hz output by the oscillation circuit
while HLMOD = 1 (sampling time is 122 µs in the case of
fosc1 = 32,768 Hz).
When SVD sampling is done with HLMOD set to 1, the
results are written to the SVDDT register with the as follow-
ing timing:
Immediately on completion of sampling in cycles of 2 Hz
output by the oscillation circuit while HLMOD = 1.
Consequently, after HLMOD is set to 1, the new detected
result is written in 2 Hz.
In the heavy load protection mode, the consumed current
becomes larger. Unless necessary, do not select the heavy
load protection mode with the software.
HLMOD
Address Comment
Register
D3 D2 D1 D0 Name SR 1 0
0FAH
HLMOD 0 SVDDT SVDON
HLMOD
0
SVDDT
SVDON
0
0
0 ON OFF
Heavy load protection mode register
Supply voltage detector data
Supply voltage detector ON/OFF
RR/W R/W
Heavy
load
Supply
voltage
low
Normal
load
Supply
voltage
normal