Specifications

I-66 EPSON S1C62N82 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)

The following explains the timing when the SVD circuit

writes the result of supply voltage detection to the SVDDT

The result of supply voltage detection is written to the

SVDDT register by the SVD circuit, and this data can be

read by the software to determine the supply voltage.

There are two methods, explained below, for executing the

detection by the SVD circuit.

(1) Sampling with HLMOD set to 1

When HLMOD is set to 1 and SVD sampling is executed,

the detection results can be written to the SVDDT regis-

ter with the following timing:

Immediately after sampling with the 2 Hz cycle output by

the oscillation circuit while HLMOD = 1 (sampling time is

122 µs in the case of fosc1 = 32,768 Hz).

Consequently, after HLMOD has been set to 1, the new

detection result is written in a 2 Hz.

(2) Sampling with SVDON set to 1

When SVDON is set to 1, SVD detection is executed. As

soon as SVDON is reset to 0, the result is loaded to in the

SVDDT register. To obtain a stable SVD detection result,

the SVD circuit must be on for at least 100 µs. So, to

obtain the SVD detection result, follow the programming

sequence below.

➀ Set SVDON to 1

➁ Maintain for 100 µs minimum

➂ Set SVDON to 0

➃ Read SVDDT

However, at 32 kHz for the S1C62N82 and S1C62L82,

the instruction cycles are long enough, so there is no

need to worry about maintaining 100 µs for SVDON = 1

in the software.

Operation of SVD

detection timing