Specifications

I-62 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)
1/100 sec stopwatch timer (0E2H)
Data (BCD) of the 1/100 sec column of the stopwatch timer
can be read. These four bits are read-only, and cannot be
written to.
After an initial reset, the timer data is set to 0H.
1/10 sec stopwatch timer (0E3H)
Data (BCD) of the 1/10 sec column of the stopwatch timer
can be read. These four bits are read-only, and cannot be
written to.
After an initial reset, the timer data is set to 0H.
Interrupt mask register (0EAH D0 and D1)
These registers mask the stopwatch timer interrupt.
When 1 is written: Enabled
When 0 is written: Masked
Reading: Valid
The interrupt mask register bits (EISW0, EISW1) are used to
mask the 10 Hz and 1 Hz interrupts, respectively. Writing
to the interrupt mask registers should be done only in the
DI status (interrupt flag = 0). Otherwise, it causes malfunc-
tion.
After an initial reset, these registers are both set to 0.
Interrupt factor flags (0EEH D0 and D1)
These flags indicate the status of the stopwatch timer inter-
rupt.
When 1 is read: Interrupt has occurred
When 0 is read: Interrupt has not occurred
Writing: Invalid
The interrupt factor flags (ISW0, ISW1) correspond to the 10
Hz and 1 Hz interrupts, respectively. With these flags, the
software can determine whether a stopwatch timer interrupt
has occurred. However, regardless of the interrupt mask
register setting, these flags are set to 1 by the timer over-
flow. They are reset when the register is read by the soft-
ware.
SWL0–SWL3
EISW0, EISW1
SWH0–SWH3
ISW0, ISW1