Specifications

S1C62N82 TECHNICAL HARDWARE EPSON I-55
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
Table 4.7.1 shows the clock timer control bits and their
addresses.
Control of clock
timer
Table 4.7.1 Control bits of clock timer
Address Comment
Register
D3 D2 D1 D0 Name SR 1 0
0E4H
TM3 TM2 TM1 TM0
R
TM3
TM2
TM1
TM0
–
–
–
–
Timer data (clock timer 2 Hz)
Timer data (clock timer 4 Hz)
Timer data (clock timer 8 Hz)
Timer data (clock timer 16 Hz)
High
High
High
High
Low
Low
Low
Low
0EBH
0 EIT2 EIT8 EIT32
R
0
EIT2
EIT8
EIT32
0
0
0
Enable
Enable
Enable
Mask
Mask
Mask
Interrupt mask register (clock timer 2 Hz)
Interrupt mask register (clock timer 8 Hz)
Interrupt mask register (clock timer 32 Hz)
R/W
0EFH
0 IT2 IT8 IT32
0
IT2
IT8
IT32
0
0
0
Yes
Yes
Yes
No
No
No
Interrupt factor flag (clock timer 2 Hz)
Interrupt factor flag (clock timer 8 Hz)
Interrupt factor flag (clock timer 32 Hz)
R
0F9H
0 TMRST SWRUN SWRST
W
0
TMRST
SWRUN
SWRST
Reset
0
Reset
Clock timer reset
Stopwatch timer RUN/STOP
Stopwatch timer reset
Reset
Run
Reset
–
Stop
–
R/W WR