Specifications

S1C62N82 TECHNICAL HARDWARE EPSON I-33
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
K00–K03, K10
Table 4.3.1 (b) Input port control bits (2)
Input port data (0E0H, 0E1H D0)
The input data of the input port pins can be read with these
registers.
When 1 is read: High level
When 0 is read: Low level
Writing: Invalid
The value read is 1 when the pin voltage of the five bits of
the input ports (K00–K03, K10) goes high (VDD), and 0 when
the voltage goes low (VSS). These bits are reading, so writing
cannot be done.
Address Comment
Register
D3 D2 D1 D0 Name SR 1 0
0E8H
0E9H
EIK03 EIK02 EIK01 EIK00
0 0 0 EIK10
R
R/W
EIK03
EIK02
EIK01
EIK00
0
0
0
0
0
0
0
EIK10
0
Interrupt mask register (K10)
Interrupt mask register (K03)
Interrupt mask register (K02)
Interrupt mask register (K01)
Interrupt mask register (K00)
Enable
Enable
Enable
Enable
Mask
Mask
Mask
Mask
Enable Mask
R/W
0EDH
00IK1IK0
R
0
0
IK1
IK0
0
0
Interrupt factor flag (K10)
Interrupt factor flag (K00–K03)
Yes
Yes
No
No