Specifications

S1C62N82 TECHNICAL HARDWARE EPSON I-29
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
Interrupt mask registers Input comparison registers
EIK03 EIK02 EIK01 EIK00 KCP03 KCP02 KCP01 KCP00
1110 1010
With the above setting, an interrupt for K00–K03 occurs under
the following conditions.
Input ports
(1) K03 K02 K01 K00
1010 (Initial value)
↓
(2) K03 K02 K01 K00
1011
↓
(3) K03 K02 K01 K00
0011
↓
(4) K03 K02 K01 K00
0111
↓
(5) K03 K02 K01 K00
1011
Fig. 4.3.3
Example of interrupt of
K00–K03
→ Interrupt generated
K00 is masked, so the three
bits of K01–K03 cease to
match those of the input
comparison register KCP01–
KCP03, and an interrupt
occurs.
K00 is masked by the interrupt mask register (EIK00), so an
interrupt does not occur at (2). At (3), K03 changes to 0; the
data of the pin that is interrupt-enabled no longer matches
the data of the input comparison register, so an interrupt
occurs. As already explained, the condition for the interrupt
to occur is the change in the port data and contents of the
input comparison register so they no longer match. Hence,
in (4) or (5), when the nonmatching pattern changes to
another nonmatching pattern or matching pattern, an
interrupt does not occur. Also, pins that have been masked
for interrupt do not affect the conditions for interrupt gen-
eration.